# US 12,015,085 B2 · Method of manufacturing a semiconductor device including etching polysilicon > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,085 B2 - Document ID: US12015085B2 - Status: Granted - Kind: B2 - Application number: 17/874,281 - Filed: 2022-07-26 - Published: 2022-11-10 - Granted: 2024-06-18 - Earliest claimed: 2020-07-10 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yan-Ting Shen; Chia-Chi Yu; Chih-Teng Liao; Yu-Li Lin; Chih Hsuan Cheng; Tzu-Chan Weng - Web page: https://patentgrep.com/patent/US12015085B2 ## CPC - H10D 30/62: Fin field-effect transistors [FinFET] - H10P 50/268: {of silicon-containing layers} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/6219: {characterised by the source or drain electrodes} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10P 50/71: {using masks for conductive or resistive materials} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, comprising: forming a fin structure protruding from an isolation insulating layer disposed over a substrate; forming a sacrificial gate dielectric layer over the fin structure; forming a polysilicon layer over the sacrificial gate dielectric layer; forming a mask pattern over the polysilicon layer; patterning the polysilicon layer into a sacrificial gate electrode using the mask pattern as an etching mask; and replacing the sacrificial gate dielectric layer and the sacrificial gate electrode with a metal gate structure including a high-k dielectric layer and a metal gate electrode, wherein: the patterning the poly silicon layer includes: forming a coating material layer on an inner wall of an etching chamber; loading the substrate with the polysilicon layer into the etching chamber; and etching the polysilicon layer by plasma dry etching, one or more etching conditions of the polysilicon etching are adjusted so that the metal gate structure has: a first width W1 at a first level H1 from an upper surface of the isolation insulating layer, and a second width W2 at a second level H2 from the upper surface of the isolation insulating layer, the first level corresponds to a level of a top of the fin structure, H2 equal to 0.45 H1, and the first width W1 is different from the second width W2. ### Claim 2 (depends on 1) The method of claim 1, wherein during the etching the polysilicon layer, the coating material layer is partially removed and a part of the inner wall is exposed. ### Claim 3 (depends on 1) The method of claim 1, wherein W1 is greater than W2. ### Claim 4 (depends on 3) The method of claim 3, wherein W2/W1 is in a range from 0.738 to 0.81. ### Claim 5 (depends on 1) The method of claim 1, wherein W1 is smaller than W2. ### Claim 6 (depends on 5) The method of claim 5, wherein W2/W1 is in a range from 1.17 to 1.27. ### Claim 7 (depends on 1) The method of claim 1, wherein the coating material layer includes a polymer. ### Claim 8 (depends on 7) The method of claim 7, wherein the coating material layer includes SixOy and is formed from a gas containing a silicon source gas and oxygen. ### Claim 9 (depends on 8) The method of claim 8, wherein the silicon source gas is SiCl4. ### Claim 10 A method of manufacturing a semiconductor device, comprising: forming a fin structure protruding from an isolation insulating layer disposed over a substrate; forming a sacrificial gate dielectric layer over the fin structure; forming a polysilicon layer over the sacrificial gate dielectric layer; forming a mask pattern over the polysilicon layer; patterning the polysilicon layer into a sacrificial gate electrode using the mask pattern as an etching mask; and replacing the sacrificial gate dielectric layer and the sacrificial gate electrode with a metal gate structure including a high-k dielectric layer and a metal gate electrode, wherein: the patterning the polysilicon layer includes: forming a coating material layer on an inner wall of an etching chamber; loading the substrate with the polysilicon layer into the etching chamber; and etching the polysilicon layer by plasma dry etching, one or more etching conditions of the polysilicon layer are adjusted so that the metal gate structure has: a lower portion below a level of a top of the fin structure and above an upper surface of the isolation insulating layer and an upper portion above the lower portion, and the lower portion has a pincushion shape, wherein during the etching the polysilicon layer, the coating material layer is partially removed and a part of the inner wall is exposed. ### Claim 11 (depends on 10) The method of claim 10, wherein: the lower portion of the metal gate structure has: a first width W1 at a first level H1 from the upper surface of the isolation insulating layer, a second width W2 at a second level H2 from the upper surface of the isolation insulating layer, and a third width W3 at the upper surface of the isolation insulating layer, the first level corresponds to the level of the top of the fin structure, H2 equal to 0.45 H1, and the second width W2 is smaller than the first width W1 and the third width W3. ### Claim 12 (depends on 10) The method of claim 10, wherein the forming the coating material comprises at least one condition of a pressure in a range from 5 mTorr to 10 mTorr or a flow ratio of SiCl4 to oxygen in a range from 0.05 to 0.2. ### Claim 13 (depends on 10) The method of claim 10, wherein the coating material layer includes SixOy and is formed from a gas mixture of SiCl4, O2 and Ar. ### Claim 14 (depends on 10) The method of claim 10, wherein the coating material layer includes a polymer. ### Claim 15 A method of manufacturing a semiconductor device, comprising: forming a fin structure protruding from an isolation insulating layer disposed over a substrate; forming a sacrificial gate dielectric layer over the fin structure; forming a polysilicon layer over the sacrificial gate dielectric layer; forming a mask pattern over the polysilicon layer; patterning the polysilicon layer into a sacrificial gate electrode using the mask pattern as an etching mask; and replacing the sacrificial gate dielectric layer and the sacrificial gate electrode with a metal gate structure including a high-k dielectric layer and a metal gate electrode, wherein: the patterning the poly silicon layer includes: forming a coating material layer on an inner wall of an etching chamber; and etching the polysilicon layer by plasma dry etching in the etching chamber, one or more etching conditions of the polysilicon etching are adjusted so that the metal gate structure has: a first width W1 at a first level H1 from an upper surface of the isolation insulating layer, a second width W2 at a second level H2 from the upper surface of the isolation insulating layer, and a third width W3 at the upper surface of the isolation insulating layer, the first level corresponds to a level of a top of the fin structure, H2 equal to 0.45 H1, and the first width W1, the second width W2 and the third width W3 are different from each other. ### Claim 16 (depends on 15) The method of claim 15, wherein during the etching the polysilicon layer, the coating material layer is etched at an etching rate is in a range from 0.5 nm/s to 1.0 nm/s. ### Claim 17 (depends on 16) The method of claim 16, wherein during the etching the polysilicon layer, a part of the inner wall is exposed. ### Claim 18 (depends on 17) The method of claim 17, wherein a thickness of the coating material layer as formed is in a range from 10 nm to 50 nm. ### Claim 19 (depends on 15) The method of claim 15, wherein W1