# US 12,015,084 B2 · Field effect transistors with gate fins and method of making the same

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- Number: US 12,015,084 B2
- Document ID: US12015084B2
- Status: Granted
- Kind: B2
- Application number: 17/474,760
- Filed: 2021-09-14
- Published: 2023-03-16
- Granted: 2024-06-18
- Earliest claimed: 2021-09-14
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Mitsuhiro Togo; Takashi Kobayashi; Sudarshan Narayanan
- Web page: https://patentgrep.com/patent/US12015084B2

## CPC

- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.

## Claims

### Claim 1

A field effect transistor, comprising:
at least one line trench extending downward from a top surface of a first transistor active region located in a substrate, and laterally extending along a first horizontal direction;
a gate dielectric contacting a bottom surface and sidewalls of each of the at least one line trench and comprising a planar gate dielectric portion overlying the substrate, at least one bottom gate dielectric portion contacting a bottom surface of a respective one of the at least one line trench, and vertically-extending gate dielectric portions contacting sidewalls of the at least one line trench and connecting the planar gate dielectric portion and a respective one of the at least one bottom gate dielectric portion;
a gate electrode comprising a planar gate electrode portion that overlies the planar gate dielectric portion and at least one gate electrode fin portion located within the at least one line trench;
a dielectric gate spacer laterally surrounding the gate electrode and comprising at least one pair of downward-protruding portions vertically extending into the at least one line trench, wherein each downward-protruding portion of the dielectric gate spacer comprises a respective bottom surface that contacts a top surface segment of a respective bottom gate dielectric portion of the gate dielectric; and
a source extension region in contact with end segments of a bottom surface and sidewalls of the at least one line trench and contacting a bottom surface of the planar gate dielectric portion.

### Claim 2 (depends on 1)

The field effect transistor of claim 1, wherein the dielectric gate spacer contacts a segment of a top surface of the planar gate dielectric portion and sidewalls of vertically-extending portions of the gate dielectric that are located in the at least one line trench.

### Claim 3 (depends on 1)

The field effect transistor of claim 1, wherein bottom surfaces of the at least one pair of downward-protruding portions of the dielectric gate spacer are located within a same horizontal plane as a bottom surface of each of the at least one gate electrode fin portion.

### Claim 4 (depends on 1)

The field effect transistor of claim 1, wherein the at least one pair of downward-protruding portions of the dielectric gate spacer contacts sidewalls the at least one gate electrode fin portion.

### Claim 5 (depends on 4)

The field effect transistor of claim 4, wherein interfaces between the at least one pair of downward-protruding portions of the dielectric gate spacer and the at least one gate electrode fin portion are perpendicular to the first horizontal direction.

### Claim 6 (depends on 1)

The field effect transistor of claim 1, wherein:
the planar gate electrode portion has widthwise gate sidewalls that are perpendicular to the first horizontal direction and laterally spaced apart along the first horizontal direction by a gate length; and
the at least one gate electrode fin portion has respective widthwise fin sidewalls that are perpendicular to the first horizontal direction and laterally spaced apart along the first horizontal direction by the gate length.

### Claim 7 (depends on 6)

The field effect transistor of claim 6, wherein each of the widthwise fin sidewalls is vertically coincident with a respective one of the widthwise gate sidewalls.

### Claim 8 (depends on 1)

The field effect transistor of claim 1, further comprising a deep source region and a deep drain region located in the substrate and laterally spaced from each other by the at least one line trench, wherein the source extension region is adjoined to the deep source region to provide a source region.

### Claim 9 (depends on 8)

The field effect transistor of claim 8, wherein a bottommost surface of the source extension region is located at a greater depth than a bottom surface of the deep source region from a horizontal plane including an interface between the substrate and the planar gate dielectric portion.

### Claim 10 (depends on 9)

The field effect transistor of claim 9, wherein a bottom surface of a horizontally-extending portion of the source extension region that is laterally offset from the at least one line trench is located at a lesser depth than the bottom surface of the deep source region from the horizontal plane.

### Claim 11 (depends on 1)

The field effect transistor of claim 1, wherein the gate dielectric contacts all surfaces of the at least one line trench.

### Claim 12 (depends on 1)

The field effect transistor of claim 1, wherein the at least one line trench comprises a plurality of line trenches each having a respective pair of lengthwise sidewalls that laterally extend along the first horizontal direction and laterally spaced from each other along a second horizontal direction that is perpendicular to the first horizontal direction.

### Claim 13 (depends on 12)

The field effect transistor of claim 12, wherein the planar gate electrode portion comprises:
a pair of lengthwise sidewalls that laterally extend along the first horizontal direction; and
a pair of widthwise sidewalls that laterally extend along the second horizontal direction and having a respective bottom edge that coincides with a top edge of a respective sidewall of the gate dielectric.

### Claim 14 (depends on 1)

The field effect transistor of claim 1, wherein each of the downward-protruding portions of the dielectric gate spacer further comprises a respective first sidewall that vertically extends from a first edge of the top surface segment of the respective bottom gate dielectric portion of the gate dielectric to an edge of a top surface of the gate electrode, and a respective second sidewall that vertically extends from a second edge of the top surface segment of the respective bottom gate dielectric portion of the gate dielectric to an inner periphery of a top surface of the planar gate dielectric portion.

### Claim 15

A method of forming field effect transistor, comprising:
forming at least one line trench in a transistor active region in a semiconductor substrate;
forming a gate dielectric in the at least one line trench and over a top surface of the semiconductor substrate, wherein the gate dielectric comprises a planar gate dielectric portion overlying the substrate, at least one bottom gate dielectric portion contacting a bottom surface of a respective one of the at least one line trench, and vertically-extending gate dielectric portions contacting sidewalls of the at least one line trench and connecting the planar gate dielectric portion and a respective one of the at least one bottom gate dielectric portion;
forming a gate electrode over the gate dielectric, wherein the gate electrode comprises a planar gate electrode portion that overlies the transistor active region and at least one gate electrode fin portion located within a center portion of the at least one line trench;
forming a dielectric gate spacer around the gate electrode, wherein the dielectric gate spacer comprises downward-protruding portions vertically extending into a respective end portion of the at least one line trench, wherein each downward-protruding portion of the dielectric gate spacer comprises a respective bottom surface that contacts a top surface segment of a respective bottom gate dielectric portion of the gate dielectric; and
forming a source region and a drain region in the semiconductor substrate by implanting electrical dopants, wherein the source region comprises a source extension region having a bottommost surface that underlies a horizontal plane including each bottom surface of the at least one line trench.

### Claim 16 (depends on 15)

The method of claim 15, wherein the at least one gate electrode fin portion and a respective pair of downward-protruding portions are formed in the at least one line trench.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
forming a gate dielectric layer directly on all surfaces of the at least one line trench and on a top surface of the semiconductor substrate;
depositing at least one gate electrode material layer over the gate dielectric layer; and
patterning the at least one gate electrode material layer by performing an anisotropic etch process that etches unmasked portions of the at least one gate electrode material layer selective to the gate dielectric layer, wherein:
a patterned portion of the at least one gate electrode material layer comprises the gate electrode; and
a pair of voids is formed within each line trench of the at least one line trench.

### Claim 18 (depends on 17)

The method of claim 17, wherein the dielectric gate spacer is formed by depositing at least one dielectric spacer material layer around the gate electrode and in the voids in the at least one line trench, and by anisotropically etching the at least one dielectric spacer material layer.

### Claim 19 (depends on 15)

The method of claim 15, wherein:
the at least one line trench comprises a plurality of line trenches including a respective pair of lengthwise sidewalls that laterally extend along a first horizontal direction and laterally spaced apart along a second horizontal direction; and
each of plurality of line trenches comprises a respective upper periphery that coincides with a periphery of a respective opening in the top surface of the semiconductor substrate.

### Claim 20 (depends on 15)

The method of claim 15, wherein each of the downward-protruding portions of the dielectric gate spacer further comprises a respective first sidewall that vertically extends from a first edge of the top surface segment of the respective bottom gate dielectric portion of the gate dielectric to an edge of a top surface of the gate electrode, and a respective second sidewall that vertically extends from a second edge of the top surface segment of the respective bottom gate dielectric portion of the gate dielectric to an inner periphery of a top surface of the planar gate dielectric portion.