# US 12,015,079 B2 · Transistor with single termination trench having depth more than 10 microns

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- Number: US 12,015,079 B2
- Document ID: US12015079B2
- Status: Granted
- Kind: B2
- Application number: 17/460,747
- Filed: 2021-08-30
- Published: 2023-03-02
- Granted: 2024-06-18
- Earliest claimed: 2021-08-30
- Assignees: Polar Semiconductor, Inc.
- Applicants: Polar Semiconductor, LLC
- Inventors: Noel Hoilien; Peter West; Rajesh Appat
- Web page: https://patentgrep.com/patent/US12015079B2

## CPC

- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 12/01: Manufacture or treatment
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D 64/111: {Field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer; depositing a second epitaxial layer on the first epitaxial layer; forming a single termination trench in the second epitaxial layer; and filling the termination trench with a dielectric. A depth of the termination trench is greater than 10 microns. In another aspect, a transistor includes a first epitaxial layer; a second epitaxial layer on the first epitaxial layer; and a single termination trench in the second epitaxial layer. The termination trench is greater than 10 microns and is filled with a dielectric.

## Claims

### Claim 1

A method of fabricating a transistor, comprising:
depositing a first epitaxial layer;
depositing a second epitaxial layer on the first epitaxial layer;
ion implanting the second epitaxial layer to form a base layer along a top surface of the second epitaxial layer and implanting a source into the base layer, wherein the base layer is a base of the transistor;
forming a single termination trench in the second epitaxial layer by etching the second epitaxial layer through the base layer so that the base layer is on either side of the trench, wherein a depth of the termination trench is greater than 10 microns;
driving the source implanting by heating the source;
filling the termination trench with a dielectric material,
wherein the base layer on either side of the trench is in direct contact with the dielectric material; and
depositing a contact glass on the dielectric material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the depth of the termination trench is between 20 and 60 microns in depth.

### Claim 3 (depends on 2)

The method of claim 2, wherein the depth of the termination trench is about 40 microns in depth with a 1- to 2-micron variation.

### Claim 4 (depends on 1)

The method of claim 1, wherein the transistor is a bipolar junction transistor or a metal-oxide-semiconductor field-effect transistor (MOSFET).

### Claim 5 (depends on 4)

The method of claim 4, wherein the transistor is an insulated-gate bipolar junction transistor.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming a single termination trench in the second epitaxial layer comprises forming a single termination trench in the second epitaxial layer and the first epitaxial layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein depositing the first epitaxial layer comprises depositing the first epitaxial layer on a doped substrate, wherein the doped substrate is a collector of the transistor.

### Claim 8 (depends on 7)

The method of claim 7, wherein the doped substrate is a P+ doped substrate.

### Claim 9 (depends on 7)

The method of claim 7, wherein forming a single termination trench in the second epitaxial layer comprises forming a single termination trench in the second epitaxial layer and the first epitaxial layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming a single termination trench in the second epitaxial layer and the first epitaxial layer comprises forming a single termination trench in the second epitaxial layer, the first epitaxial layer and the doped substrate.

### Claim 11 (depends on 1)

The method of claim 1, further comprising depositing a metal layer on the contact glass.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming cell trenches in the second epitaxial layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein depositing the contact glass further comprises depositing the contact glass on the cell trenches.

### Claim 14 (depends on 13)

The method of claim 13, wherein depositing the metal layer further comprises depositing the metal layer on the cell trenches.

### Claim 15 (depends on 1)

The method of claim 1, wherein the contact glass includes a borophosphosilicate glass (BPSG) and a undoped silane glass (USG).

### Claim 16 (depends on 11)

The method of claim 11, further comprising etching the metal layer.

### Claim 17 (depends on 11)

The method of claim 11, wherein the metal layer includes aluminum silicon.