# US 12,015,078 B2 · Manufacturing method of semiconductor power device

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- Number: US 12,015,078 B2
- Document ID: US12015078B2
- Status: Granted
- Kind: B2
- Application number: 17/622,021
- Filed: 2020-11-12
- Published: 2023-08-24
- Granted: 2024-06-18
- Earliest claimed: 2020-10-20
- Assignees: Suzhou Oriental Semiconductor Co., Ltd.
- Applicants: Suzhou Oriental Semiconductor Co., Ltd.
- Inventors: Wei Liu; Zhenyi Xu; Zhendong Mao; Xin Wang
- Web page: https://patentgrep.com/patent/US12015078B2

## CPC

- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/01: Manufacture or treatment
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method of a semiconductor power device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer, a second insulating layer, and a third insulating layer as a mask to form a second groove in the n-type substrate. A fourth insulating layer and a gate are formed in the second groove.

## Claims

### Claim 1

A manufacturing method of a semiconductor power device, comprising:
forming a first insulating layer on an n-type substrate and etching the first insulating layer to form an opening;
forming an insulating sidewall in the opening;
etching the n-type substrate using the first insulating layer and the insulating sidewall as a mask to form a first groove in the n-type substrate;
forming a second insulating layer and a shield gate in the first groove;
forming a third insulating layer on a surface of the shield gate;
etching off the insulating sidewall; and etching the n-type substrate using the first insulating layer, the second insulating layer, and the third insulating layer as a mask to form a second groove in the n-type substrate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a fourth insulating layer and a gate in the second groove such that the gate is isolated from the shield gate by the second insulating layer;
etching off the first insulating layer and the third insulating layer;
forming a p-type body region in the n-type substrate; and
forming an n-type source region in the p-type body region.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
etching off the first insulating layer, the third insulating layer, and a part of the second insulating layer which is located at a position of a sidewall of the second groove;
forming a fourth insulating layer and a gate in the second groove such that the gate is isolated from the shield gate by the fourth insulating layer;
forming a p-type body region in the n-type substrate; and
forming an n-type source region in the p-type body region.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first insulating layer comprises a silicon oxide layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second insulating layer is a silicon oxide layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the third insulating layer is a silicon oxide layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the insulating sidewall is a silicon nitride layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein an etching method combining anisotropic etching and isotropic etching is performed when the second groove is formed by etching.

### Claim 9 (depends on 1)

The method of claim 1, wherein a depth of the second groove is less than a depth of the first groove.