# US 12,015,075 B2 · Methods of manufacturing high electron mobility transistors having a modified interface region

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,015,075 B2
- Document ID: US12015075B2
- Status: Granted
- Kind: B2
- Application number: 17/325,628
- Filed: 2021-05-20
- Published: 2022-11-24
- Granted: 2024-06-18
- Earliest claimed: 2021-05-20
- Assignees: MACOM Technology Solutions Holdings, Inc.
- Applicants: Wolfspeed, Inc.
- Inventors: Kyle Bothe; Joshua Bisges
- Web page: https://patentgrep.com/patent/US12015075B2

## CPC

- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/01: Manufacture or treatment
- H10D 64/111: {Field plates}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/411: {for FETs}
- H10P 50/646: {of Group III-V materials}
- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- H10W 10/01: {Manufacture or treatment}
- H10W 72/00: Interconnections or connectors in packages
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10P 14/6319: {Formation by plasma treatments, e.g. plasma oxidation of the substrate}
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 95/904: {of Group III-V semiconductors}
- H10W 72/07554: {changes in dispositions}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 76/134: having other interconnections parallel to the conductive base
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/759: {between a chip and a laterally-adjacent discrete passive device}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.

## Claims

### Claim 1

A method of forming a high electron mobility transistor (HEMT), comprising:
providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate;
forming a first insulating layer on the barrier layer; and
forming a gate contact, a source contact, and a drain contact on the barrier layer,
wherein an interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.

### Claim 2 (depends on 1)

The method of claim 1, wherein a bottom surface of the gate contact is laterally offset from the modified interface region by 10 to 400 nm.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the first insulating layer on the barrier layer comprises a use of physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), and/or thermolytic deposition.

### Claim 4 (depends on 1)

The method of claim 1, further comprising wet etching an upper surface of the barrier layer in an acidic and/or basic chemical bath prior to forming the first insulating layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising, prior to forming the first insulating layer, performing an ion bombardment of the barrier layer, performing a plasma nitridation of the barrier layer, performing a plasma oxidation of the barrier layer, performing an H2 plasma treatment of the barrier layer, and/or annealing the barrier layer in a gas environment.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a spacer between the modified interface region and the gate contact.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the spacer comprises:
etching a hole in the first insulating layer; and
forming the spacer on a sidewall of the hole and on the barrier layer,
wherein forming the gate contact comprises forming at least a portion of the gate contact on a sidewall of the spacer in the hole.

### Claim 8 (depends on 6)

The method of claim 6, wherein an interface between the spacer and the barrier layer comprises an interface characteristic that is different from the modified interface region.

### Claim 9

A method of forming a high electron mobility transistor (HEMT), comprising:
providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate;
forming a first insulating layer on the barrier layer;
forming a gate contact on the barrier layer, at least a portion of the gate contact within the first insulating layer; and
providing a modified interface region between the first insulating layer and the barrier layer that is laterally separated from a bottom surface of the gate contact.

### Claim 10 (depends on 9)

The method of claim 9, wherein the modified interface region is laterally separated from the bottom surface of the gate contact by 10 to 400 nm.

### Claim 11 (depends on 9)

The method of claim 9, further comprising:
etching a hole in the first insulating layer; and
forming a spacer on a sidewall of the hole and on the barrier layer,
wherein forming the gate contact comprises forming at least a portion of the gate contact on a sidewall of the spacer in the hole.

### Claim 12 (depends on 11)

The method of claim 11, wherein an interface between the spacer and the barrier layer comprises a trap concentration that is different from a trap concentration of the modified interface region.

### Claim 13 (depends on 9)

The method of claim 9, wherein providing the modified interface region comprises, prior to forming the first insulating layer, wet etching an upper surface of the barrier layer in an acidic and/or basic chemical bath, performing an ion bombardment of the barrier layer, performing a plasma nitridation of the barrier layer, performing a plasma oxidation of the barrier layer, performing an H2 plasma treatment of the barrier layer, and/or annealing the barrier layer in a gas environment.

### Claim 14 (depends on 9)

The method of claim 9, wherein a thickness of the first insulating layer is between 80 nm and 120 nm.

### Claim 15 (depends on 9)

The method of claim 9, wherein a sheet resistance of a drain access region and/or a source access region of the semiconductor structure beneath the modified interface region is between 300 and 400 Ω/sq.

### Claim 16

A method of forming a high electron mobility transistor (HEMT), comprising:
providing a semiconductor structure comprising a channel layer on a substrate and a barrier layer on the channel layer;
forming a first insulating layer on the barrier layer and etching an opening in the first insulating layer, the first insulating layer comprising a modified interface region in an interface between the first insulating layer and the barrier layer;
forming a spacer on the barrier layer in the opening in the first insulating layer; and
forming a gate contact on the barrier layer and the spacer in the opening in the first insulating layer,
wherein an interface between the spacer and the barrier layer comprises a trap concentration and/or surface potential that is different from a trap concentration and/or surface potential of the modified interface region.

### Claim 17 (depends on 16)

The method of claim 16, further comprising thinning the substrate.

### Claim 18 (depends on 16)

The method of claim 16, wherein a bottom corner of the gate contact is offset from the modified interface region by the spacer.

### Claim 19 (depends on 16)

The method of claim 16, wherein a thickness of the first insulating layer is between 80 nm and 120 nm.

### Claim 20 (depends on 16)

The method of claim 16, wherein a width of a bottom surface of the spacer that is adjacent the barrier layer is 10 to 400 nm.

### Claim 21 (depends on 16)

The method of claim 16, wherein forming the first insulating layer comprising the modified interface region comprises:
wet etching an upper surface of the barrier layer in an acidic and/or basic chemical bath, performing a buffered oxide etch (BOE) of the upper surface of the barrier layer, performing an ion bombardment of the barrier layer, performing a plasma nitridation of the barrier layer, performing a plasma oxidation of the barrier layer, performing an H2 plasma treatment of the barrier layer, and/or annealing the barrier layer in a gas environment; and
depositing a passivation layer on the barrier layer.