# US 12,015,071 B2 · Air spacers around contact plugs and method forming same

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- Number: US 12,015,071 B2
- Document ID: US12015071B2
- Status: Granted
- Kind: B2
- Application number: 17/805,552
- Filed: 2022-06-06
- Published: 2022-09-29
- Granted: 2024-06-18
- Earliest claimed: 2019-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Huang Huang; Ming-Jhe Sie; Yih-Ann Lin; An Chyi Wei; Ryan Chia-Jen Chen
- Web page: https://patentgrep.com/patent/US12015071B2

## CPC

- H10D 64/679: {comprising air gaps}
- H10W 20/076: {in via holes or trenches}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 50/268: {of silicon-containing layers}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

## Claims

### Claim 1

A device comprising:
a gate stack;
a source/drain region on a side of the gate stack;
a silicide region over the source/drain region;
a contact plug over the silicide region;
a dielectric isolation layer encircling the contact plug; and
an air spacer encircling the dielectric isolation layer.

### Claim 2 (depends on 1)

The device of claim 1 further comprising a contact etch stop layer, wherein the source/drain region comprises a top surface contacting a bottom surface of the contact etch stop layer, and wherein the air spacer extends into the source/drain region, and extends to a level lower than the top surface of the source/drain region.

### Claim 3 (depends on 1)

The device of claim 1 further comprising:
a silicon layer underlying and contacting the dielectric isolation layer, wherein a sidewall of the silicon layer is exposed to the air spacer, and wherein the source/drain region is formed of a material different from the silicon layer.

### Claim 4 (depends on 3)

The device of claim 3, wherein the silicon layer is an amorphous silicon layer.

### Claim 5 (depends on 3)

The device of claim 3, wherein the silicon layer is a polysilicon layer.

### Claim 6 (depends on 1)

The device of claim 1, wherein the air spacer further extends directly under the dielectric isolation layer.

### Claim 7 (depends on 1)

The device of claim 1, wherein the air spacer comprises a portion forming a full ring fully encircling the dielectric isolation layer.

### Claim 8 (depends on 1)

The device of claim 1 further comprising an etch stop layer, wherein the etch stop layer comprises:
a first portion overlapping the contact plug; and
a second portion overlapping the air spacer, wherein a bottom surface of the second portion is exposed to the air spacer.

### Claim 9

A device comprising:
a gate stack;
a source/drain region on a side of the gate stack;
a silicide region over the source/drain region;
a contact plug over the silicide region;
a dielectric isolation layer forming a ring encircling the contact plug; and
an air spacer, wherein in a top view of the device, the air spacer comprises a first portion forming a full ring encircling the contact plug, and wherein a top surface of the source/drain region is exposed to the air spacer.

### Claim 10 (depends on 9)

The device of claim 9, wherein the air spacer comprises a second portion overlapped by the dielectric isolation layer.

### Claim 11 (depends on 9)

The device of claim 9 further comprising:
a silicon layer vertically between the dielectric isolation layer and the source/drain region, wherein a sidewall of the silicon layer is exposed to the air spacer, and wherein the silicon layer and the source/drain region are formed of different materials.

### Claim 12 (depends on 11)

The device of claim 11, wherein the air spacer extends lower than a bottom surface of the silicon layer.

### Claim 13 (depends on 9)

The device of claim 9, wherein the dielectric isolation layer comprises silicon and nitrogen.

### Claim 14 (depends on 9)

The device of claim 9 further comprising:
a contact etch stop layer comprising a bottom surface contacting the source/drain region; and
an inter-layer dielectric overlapping a bottom portion of the contact etch stop layer, wherein sidewalls of the contact etch stop layer and the inter-layer dielectric are exposed to the air spacer.

### Claim 15 (depends on 14)

The device of claim 14, wherein the sidewalls of the contact etch stop layer and the inter-layer dielectric exposed to the air spacer are vertically aligned with each other.

### Claim 16

A device comprising:
a bulk semiconductor substrate;
isolation regions over the bulk semiconductor substrate;
a semiconductor fin laterally between opposing portions of the isolation regions, wherein the semiconductor fin is higher than a top surface of the isolation regions;
a gate stack on the semiconductor fin;
a gate spacer on a first sidewall of the gate stack;
a dielectric region on a second sidewall of the gate spacer, wherein the dielectric region and the gate stack are on opposing sides of the gate spacer;
an air spacer, wherein the dielectric region is exposed to the air spacer;
a source/drain region comprising a sidewall, wherein an upper portion of the sidewall of the source/drain region contacts the gate spacer; and
a silicon layer overlying and contacting the source/drain region, wherein the silicon layer comprises an amorphous structure or a polysilicon structure.

### Claim 17 (depends on 16)

The device of claim 16, wherein the silicon layer comprises a first edge facing and exposed to the air spacer.

### Claim 18 (depends on 17)

The device of claim 17 further comprising a source/drain silicide region over and contacting the source/drain region, wherein the silicon layer further comprises a second edge, wherein the first edge and the second edge are opposite edges of the silicon layer, and wherein the second edge contacts the source/drain silicide region.

### Claim 19 (depends on 17)

The device of claim 17, wherein the source/drain region comprises germanium, and wherein the silicon layer is substantially free from germanium.

### Claim 20 (depends on 16)

The device of claim 16 further comprising a dielectric ring, wherein the dielectric region and the dielectric ring are on opposite sides of the air spacer, and wherein the dielectric ring is also exposed to the air spacer.