# US 12,015,069 B2 · Gate-all-around field effect transistor having multiple threshold voltages

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- Number: US 12,015,069 B2
- Document ID: US12015069B2
- Status: Granted
- Kind: B2
- Application number: 16/745,049
- Filed: 2020-01-16
- Published: 2020-08-06
- Granted: 2024-06-18
- Earliest claimed: 2017-01-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruqiang Bao; Michael A. Guillorn; Terence Hook; Robert R. Robison; Reinaldo Vega; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US12015069B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

## Claims

### Claim 1

An apparatus, comprising:
a doped conducting channel region having at least two conducting layers including an n-type dopant for an n-type work function and at least two conducting layers including a p-type dopant for a p-type work function, the two conducting layers including a silicon n-type channel and a silicon germanium p-type channel; and
a gate stack surrounding all sides of the conducting channel region, wherein the gate stack comprises:
a doped substrate;
a metal doping layer deposited directly on the doped substrate, wherein the metal doping layer is formed from a dipole; and
an adjustment oxide layer deposited directly on the metal doping layer, wherein gate stack including the metal doping layer provides at least four threshold voltages for the apparatus, the apparatus being a single transistor having a single gate structure with the at least four threshold voltages, wherein differences in the threshold voltages is attributed to the metal doping, the metal doping for the n-type work function including a metal alloy selected from the group consisting of titanium aluminum and titanium aluminum carbide.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the apparatus is an n-type field effect transistor.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the substrate comprises silicon.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the metal doping layer comprises at least one of: lanthanum, ytterbium, magnesium, an oxide of lanthanum, an oxide of ytterbium, and an oxide of magnesium.

### Claim 5 (depends on 3)

The apparatus of claim 3, further comprising:
a layer of a first barrier metal deposited directly on the adjustment oxide layer;
a layer of an n-type field effect transistor work function metal deposited directly on the layer of the first barrier metal; and
a layer of a second barrier metal deposited directly on the layer of the n-type field effect transistor work function metal.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the apparatus is a p-type field effect transistor.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the substrate comprises silicon germanium.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the silicon germanium is p-doped.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the gate stack directly contacts the doped conducting channel region.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the gate stack has a plurality of threshold voltages that comprise up to eight threshold voltages.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the doped conducting channel region comprises a plurality of conducting channels and at least some conducting channels of the plurality of conducting channels are epitaxially grown and doped in situ.

### Claim 12

An apparatus, comprising:
an n-type field effect transistor, comprising:
a first doped conducting channel region having at least four conducting layers including an n-type dopant, the at least four conducting layers comprised of silicon; and
a first gate stack surrounding all sides of the first doped conducting channel region, wherein the first gate stack comprises:
a first doped substrate;
a first metal doping layer deposited directly on the first doped substrate, wherein the first metal doping layer is formed from a dipole; and
a first adjustment oxide layer deposited directly on the first metal doping layer; and
a p-type field effect transistor, comprising:
a second doped conducting channel region having at least four conducting layers including a p-type dopant, the at least four conducting layer comprised of silicon germanium; and
a second gate stack surrounding all sides of the second doped conducting channel region, wherein the second gate stack comprises:
a second doped substrate;
a second metal doping layer deposited directly on the second doped substrate, wherein the second metal doping layer is formed from a dipole; and
a second adjustment oxide layer deposited directly on the second metal doping layer, wherein the apparatus has a plurality of threshold voltages including at least four different n-type threshold voltages for the n-type field effect transistor that are attributed to the first metal doping layer and at least four different p-type threshold voltages for the p-type field effect transistor that are attributed to the second metal doping layer, the first metal doping layer including a metal alloy selected from the group consisting of titanium aluminum and titanium aluminum carbide.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the first gate stack directly contacts the first doped conducting channel region and the second gate stack directly contacts the second conducting channel region.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein the apparatus has a plurality of threshold voltages that comprise up to eight n-type threshold voltages and up to eight p-type threshold voltages.

### Claim 15 (depends on 12)

The apparatus of claim 12, further comprising:
a layer of a first barrier metal deposited directly on the first adjustment oxide layer;
a layer of a p-type field effect transistor work function metal deposited directly on the layer of the first barrier metal; and
a layer of a second barrier metal deposited directly on the layer of the p-type field effect transistor work function metal.