# US 12,015,067 B2 · Semiconductor device and fabrication method thereof

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- Number: US 12,015,067 B2
- Document ID: US12015067B2
- Status: Granted
- Kind: B2
- Application number: 17/231,451
- Filed: 2021-04-15
- Published: 2021-12-23
- Granted: 2024-06-18
- Earliest claimed: 2020-06-19
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Nan Wang
- Web page: https://patentgrep.com/patent/US12015067B2

## CPC

- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; a gate structure on the base substrate, including a first portion in a first region and a second portion in a second region; and one or more stop layers on the base substrate and located in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region.

## Claims

### Claim 1

A semiconductor device, comprising:
a base substrate, the base substrate including a substrate and a plurality of fins discrete from each other on the substrate;
a gate structure on the base substrate, wherein the gate structure includes a first portion in a first region and a second portion in a second region, and a length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region; and
a plurality of stop layers on the base substrate and located in the first portion of the gate structure in the first region, the plurality of stop layers being made of a material including SiCBN;
wherein:
the gate structure includes a gate dielectric layer on top surfaces and sidewalls of the plurality of fins, a work function layer on the gate dielectric layer, and a gate electrode layer on the work function layer; and
the gate dielectric layer is in contact with a bottom surface of the plurality of stop layers, the work function layer and the gate electrode layer are in contact with sidewall surfaces of the plurality of stop layers.

### Claim 2 (depends on 1)

The device according to claim 1, wherein:
the plurality of fins includes a sparse region and a dense region; and
a distance between adjacent fins of the plurality of fins in the sparse region is larger than a distance between adjacent fins of the plurality of fins in the dense region.

### Claim 3 (depends on 2)

The device according to claim 2, wherein:
the first portion of the gate structure in the first region is located between the plurality of fins in the sparse region, and the second portion of the gate structure in the second region is located between the plurality of fins in the dense region.

### Claim 4 (depends on 2)

The device according to claim 2, wherein:
the length of each portion of the gate structure is a distance of each portion of the gate structure across corresponding adjacent fins of the plurality of fins along a direction perpendicular to an extending direction of the plurality of fins.

### Claim 5 (depends on 2)

The device according to claim 2, further including an isolation layer on the substrate, wherein:
the isolation layer covers a portion of sidewalls of the plurality of fins.

### Claim 6 (depends on 2)

The device according to claim 2, further including source/drain doped layers in the plurality of fins at two sides of the gate structure.

### Claim 7 (depends on 2)

The device according to claim 2, further including an interlayer dielectric layer on the source/drain doped layers and sidewalls of the gate structure.

### Claim 8

A fabrication method of a semiconductor device, comprising:
providing a base substrate, the base substrate including a substrate and a plurality of fins discrete from each other on the substrate;
forming a dummy gate structure on the base substrate, wherein the dummy gate structure including a first portion in a first region and a second portion in a second region, and a length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region;
etching part of the first portion of the dummy gate structure in the first region, to form a plurality of openings in the dummy gate structure in the first region, wherein bottoms of the plurality of openings expose a surface of the base substrate;
forming a stop layer in each opening of the plurality of openings to fill up the opening, the plurality of stop layers being made of a material including SiCBN;
removing the dummy gate structure to form a gate opening in the base substrate;
forming an initial gate structure in the gate opening; and
planarizing the initial gate structure until exposing top surfaces of the plurality of stop layers, to form a gate structure;
wherein:
the gate structure includes a gate dielectric layer on top surfaces and sidewalls of the plurality of fins, a work function layer on the gate dielectric layer, and a gate electrode layer on the work function layer; and
the gate dielectric layer is in contact with a bottom surface of the plurality of stop layers, the work function layer and the gate electrode layer are in contact with sidewall surfaces of the plurality of stop layers.

### Claim 9 (depends on 8)

The method according to claim 8, wherein:
the plurality of stop layers are formed by a chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method, or a combination thereof.

### Claim 10 (depends on 8)

The method according to claim 8, wherein each of the plurality of stop layers is formed by:
forming an initial stop layer in each opening and on a top surface of the dummy gate structure; and
planarizing the initial stop layer until exposing the top surface of the dummy gate structure.

### Claim 11 (depends on 8)

The method according to claim 8, wherein:
the plurality of fins includes a sparse region and a dense region; and
a distance between adjacent fins of the plurality of fins in the sparse region is larger than a distance between adjacent fins of the plurality of fins in the dense region.

### Claim 12 (depends on 11)

The method according to claim 11, wherein:
the first portion of the dummy gate structure in the first region is located between the plurality of fins in the sparse region, and the second portion of the dummy gate structure in the second region is located between the plurality of fins in the dense region.

### Claim 13 (depends on 11)

The method according to claim 11, wherein:
the length of each portion of the dummy gate structure is a distance of each portion of the dummy gate structure across adjacent fins of the plurality of fins along a direction perpendicular to an extending direction of the plurality of fins.

### Claim 14 (depends on 8)

The method according to claim 8, after forming the dummy gate structure and before etching part of the first portion of the dummy gate structure in the first region, further including:
forming a protective layer on a top surface of the dummy gate structure; and
forming side spacers on sidewalls of the dummy gate structure and the protective layer.

### Claim 15 (depends on 11)

The method according to claim 11, further including:
forming source/drain doped layers in the plurality of fins at two sides of the gate structure.

### Claim 16 (depends on 8)

The method according to claim 8, wherein:
the openings are formed by a dry etch process or a wet etch process.