# US 12,015,065 B2 · Tri-gate orthogonal channel transistor and methods of forming the same

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- Number: US 12,015,065 B2
- Document ID: US12015065B2
- Status: Granted
- Kind: B2
- Application number: 18/358,289
- Filed: 2023-07-25
- Published: 2023-11-16
- Granted: 2024-06-18
- Earliest claimed: 2020-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Katherine H. Chiang; Chung-Te Lin
- Web page: https://patentgrep.com/patent/US12015065B2

## CPC

- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/689: {Vertical floating-gate IGFETs}
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/05: {Making the transistor}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
forming an insulating matrix layer;
embedding a drain region and a backside gate electrode in the insulating matrix layer;
forming a backside gate dielectric layer on the backside gate electrode;
depositing a metal oxide semiconductor channel layer over the drain region and the backside gate dielectric layer;
forming a source region such that the source region contacts a first end surface of the metal oxide semiconductor channel layer;
depositing and patterning a first gate dielectric material layer on a major surface of the metal oxide semiconductor channel layer; and
forming a first gate electrode on the first gate dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising depositing a second gate dielectric layer on a second end surface of the metal oxide semiconductor channel layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second end surface is a vertical surface.

### Claim 4 (depends on 2)

The method of claim 2, further comprising a gate via cavity through the first gate electrode, the metal oxide semiconductor channel layer, and an upper portion of the insulating matrix layer, wherein the second end surface is a surface segment of a sidewall of the gate via cavity.

### Claim 5 (depends on 4)

The method of claim 4, wherein the sidewall of the gate via cavity comprises a sidewall of the drain region.

### Claim 6 (depends on 2)

The method of claim 2, further comprising depositing a second gate electrode on the second gate dielectric layer.

### Claim 7 (depends on 2)

The method of claim 2, further comprising physically exposing surfaces of first gate electrode and the drain region by etching portions of the first gate electrode and the metal oxide semiconductor channel layer, wherein the second gate dielectric layer is formed on physically exposed surfaces of the first gate electrode and the drain region.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a drain recess region in the insulating matrix layer; and
depositing a conductive material in the drain recess region and a gate recess region, wherein a portion of the conductive material filling the drain recess region comprises the drain region.

### Claim 9 (depends on 1)

The method of claim 1 further comprising:
forming a gate recess region in the insulating matrix layer;
depositing a conductive material in the gate recess region; and
patterning a portion of the conductive material in the gate recess region, wherein a patterned portion of the conductive material in the gate recess region comprises the backside gate electrode.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
forming a first portion of the source region in a recess region in the insulating matrix layer adjacent to the backside gate dielectric layer, wherein the metal oxide semiconductor channel layer is formed over the first portion of the source region; and
forming a second portion of the source region by doping a portion of the metal oxide semiconductor channel layer or by replacing a portion of the metal oxide semiconductor channel layer with a conductive material portion, wherein the second portion of the source region contacts the first portion of the source region.

### Claim 11 (depends on 1)

The method of claim 1, wherein:
a portion of the major surface of the metal oxide semiconductor channel layer is physically exposed upon depositing and patterning the first gate dielectric material layer; and
the first gate electrode is formed directly on the physically exposed portion of the major surface of the metal oxide semiconductor channel layer and directly on the first gate dielectric layer.

### Claim 12

A method of forming a semiconductor device, the method comprising:
forming a drain region, a backside gate electrode, a backside gate dielectric layer, and a first source portion in an upper portion of an insulating matrix layer;
forming a metal oxide semiconductor channel layer over the drain region, the backside gate dielectric, and the first source portion;
forming a first gate electrode over a horizontal top surface of the metal oxide semiconductor channel layer; and
forming a second gate electrode over a sidewall of the metal oxide semiconductor channel layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the second gate electrode is formed over a sidewall of the drain region.

### Claim 14 (depends on 12)

The method of claim 12, further comprising forming a gate via cavity having a straight sidewall extending from a bottom edge to a top edge through the first gate electrode, the metal oxide semiconductor channel layer, and an upper portion of the insulating matrix layer, wherein the sidewall of the metal oxide semiconductor layer and a sidewall of the drain region are exposed to the gate via cavity.

### Claim 15 (depends on 14)

The method of claim 14, further comprising forming a second gate dielectric layer directly on the sidewall of the metal oxide semiconductor layer and the sidewall of the drain region.

### Claim 16 (depends on 12)

The method of claim 12, further comprising forming a second source portion by doping a portion of the metal oxide semiconductor channel layer or by replacing a portion of the metal oxide semiconductor channel layer with a conductive material portion, wherein the second portion of a source region contacts the first portion of the source region.

### Claim 17

A method of forming a semiconductor device, the method comprising:
forming a drain region, a backside gate electrode, a backside gate dielectric layer, and a first source portion in an upper portion of an insulating matrix layer;
forming a metal oxide semiconductor channel layer over the drain region, the backside gate dielectric, and the first source portion;
forming a second source portion by doping a portion of the metal oxide semiconductor channel layer or by replacing a portion of the metal oxide semiconductor channel layer with a conductive material portion, wherein the second portion of a source region contacts the first portion of the source region; and
forming a first gate electrode over a horizontal top surface of the metal oxide semiconductor channel layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a gate via cavity through the first gate electrode, the metal oxide semiconductor channel layer, and an upper portion of the insulating matrix layer;
forming a second gate dielectric layer and a second gate electrode in the gate via cavity.

### Claim 19 (depends on 18)

The method of claim 18, wherein a sidewall of the drain region is exposed to the gate via cavity, wherein the second gate dielectric layer is formed on the sidewall of the drain region.

### Claim 20 (depends on 17)

The method of claim 17, further comprising forming and patterning a first gate dielectric layer on the horizontal top surface of the metal oxide semiconductor channel layer, wherein:
a portion of the horizontal top surface of the metal oxide semiconductor channel layer is physically exposed; and
the first gate electrode is formed on the physically exposed portion of the horizontal top surface of the metal oxide semiconductor channel layer and on a top surface of the first gate dielectric layer.