# US 12,015,063 B2 · Method of manufacturing an integrated circuit device including a fin-type active region

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- Number: US 12,015,063 B2
- Document ID: US12015063B2
- Status: Granted
- Kind: B2
- Application number: 17/707,036
- Filed: 2022-03-29
- Published: 2022-07-14
- Granted: 2024-06-18
- Earliest claimed: 2018-07-26
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Chang-yeon Lee; Jin-wook Lee; Min-chan Gwak; Kye-Hyun Baek; Hong-bae Park
- Web page: https://patentgrep.com/patent/US12015063B2

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

## Claims

### Claim 1

A method of manufacturing an integrated circuit device, the method comprising:
preparing a substrate having a device active region;
forming a fin-type active region, the fin-type active region protruding from the substrate on the device active region;
forming a gate line and source/drain regions, the gate line intersecting the fin-type active region, and the source/drain regions being located on the fin-type active region at sides of the gate line;
forming a gate insulating capping layer covering a top surface of the gate line;
forming an upper insulating layer covering the gate insulating capping layer;
forming a pair of first contact holes passing through the upper insulating layer and exposing the source/drain regions;
forming a pair of first conductive plugs filling lower portions of the pair of first contact holes, the pair of first conductive plugs being respectively connected to the source/drain regions;
forming a hard mask layer covering a top surface of each first conductive plug of the pair of first conductive plugs;
forming a second contact hole exposing the gate line by removing portions of the upper insulating layer and the gate insulating capping layer; and
forming a second conductive plug filling the second contact hole,
wherein the hard mask layer covers the top surface of each first conductive plug from a first edge of the top surface to a second edge of the top surface in a first direction, and protrudes from the top surface beyond the second edge for each first conductive plug of the pair of first conductive plugs and extends toward the second conductive plug so that a portion of the hard mask layer overhangs outside of an edge of the top surface of each first conductive plug of the pair of first conductive plugs.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein forming the second contact hole includes performing an etching process using the hard mask layer as etch masks.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein:
the hard mask layer includes a cover mask layer and a cover spacer covering a side surface of the cover mask layer, and
forming the hard mask layer includes:
forming the cover mask layer covering the top surface of each first conductive plug of the pair of first conductive plugs;
forming a protective insulating layer covering the upper insulating layer and the cover mask layer;
forming a recess space by removing portions of the protective insulating layer and the upper insulating layer and exposing a portion of the upper insulating layer; and
forming the cover spacer covering a side surface of the cover mask layer.

### Claim 4 (depends on 3)

The method as claimed in claim 3, wherein the second contact hole is in communication with the recess space.

### Claim 5 (depends on 4)

The method as claimed in claim 4, wherein:
the cover spacer overhangs from the top surface of each first conductive plug of the pair first of conductive plugs, and
the cover spacer protrudes toward the second conductive plug.

### Claim 6 (depends on 3)

The method as claimed in claim 3, wherein forming the second contact hole includes forming a side wall insulating capping layer that is a remaining portion of the upper insulating layer under the cover spacer.

### Claim 7 (depends on 6)

The method as claimed in claim 6, wherein the side wall insulating capping layer is between a top surface of the gate insulating capping layer and a bottom surface of the hard mask layer and between the pair of first conductive plugs and the second conductive plug.

### Claim 8 (depends on 6)

The method as claimed in claim 6, wherein the second conductive plug protrudes laterally toward the side wall insulating capping layer.

### Claim 9 (depends on 6)

The method as claimed in claim 6, wherein a top surface of the side wall insulating capping layer contacts a bottom surface of the cover spacer.

### Claim 10 (depends on 3)

The method as claimed in claim 3, wherein:
each of the cover mask layer and the cover spacer includes a silicon carbide material, and
the silicon carbide material of the cover spacer has a carbon content that is greater than a carbon content of the silicon carbide material of the cover mask layer.

### Claim 11 (depends on 3)

The method as claimed in claim 3, further comprising, forming an auxiliary spacer covering an inner surface of the second contact hole after forming the second contact hole and before forming the second conductive plug.

### Claim 12

A method of manufacturing an integrated circuit device, the method comprising:
preparing a substrate having a device active region;
forming a fin-type active region, the fin-type active region protruding from the substrate on the device active region;
forming a gate line and source/drain regions, the gate line intersecting the fin-type active region, and the source/drain regions being located on the fin-type active region at sides of the gate line;
forming a gate insulating capping layer covering a top surface of the gate line;
forming an upper insulating layer covering the gate insulating capping layer;
forming a pair of first contact holes passing through the upper insulating layer and exposing the plurality of source/drain regions;
forming a pair of first conductive plugs filling lower portions of the pair of first contact holes, the pair of first conductive plugs being respectively connected to the source/drain regions;
forming a cover mask layer covering a top surface of each first conductive plug of the pair of first conductive plugs;
forming a protective insulating layer covering the upper insulating layer and the cover mask layer;
forming a recess space by removing portions of the protective insulating layer and the upper insulating layer and exposing a portion of the upper insulating layer;
forming a cover spacer covering a side surface of the cover mask layer;
forming a second contact hole exposing the gate line by removing portions of the upper insulating layer and gate insulating capping layer by using the cover mask layer and the cover spacer as etch masks; and
forming a second conductive plug filling the second contact hole.

### Claim 13 (depends on 12)

The method as claimed in claim 12, wherein, after forming the second contact hole, a side wall insulating capping layer that is a remaining portion of the upper insulating layer, is located between a top surface of the gate insulating capping layer and a bottom surface of the cover spacer.

### Claim 14 (depends on 13)

The method as claimed in claim 13, wherein the bottom surface of the cover spacer is at a same level as the top surface of each first conductive plug of the pair of first conductive plugs.

### Claim 15 (depends on 13)

The method as claimed in claim 13, wherein the bottom surface of the cover spacer is at a level that is higher than a level of the top surface of each first conductive plug of the pair of first conductive plugs.

### Claim 16 (depends on 13)

The method as claimed in claim 13, wherein the bottom surface of the cover spacer is at a level that is lower than a level of the top surface of each first conductive plug of the pair of first conductive plugs.

### Claim 17 (depends on 12)

The method as claimed in claim 12, wherein a top surface of the cover mask layer is at a same level as a top surface of the second conductive plug.

### Claim 18 (depends on 12)

The method as claimed in claim 12, wherein the cover spacer overhangs from the top surface of each first conductive plug of the pair of first conductive plugs and protrudes toward the second conductive plug.

### Claim 19 (depends on 12)

The method as claimed in claim 12, wherein forming the cover spacer includes:
forming a preliminary spacer layer covering a top surface of the protective insulating layer and an inner surface and a bottom surface of the recess space, and
removing a portion of the preliminary spacer layer by performing anisotropic etching.

### Claim 20 (depends on 12)

The method as claimed in claim 12, wherein forming the second conductive plug includes:
sequentially forming a second conductive barrier layer and a second conductive core layer filling the second contact hole in the recess space; and
removing the protective insulating layer and portions of the second conductive barrier layer and the second conductive core layer to expose a top surface of the cover mask layer.