# US 12,015,062 B2 · Integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,062 B2 - Document ID: US12015062B2 - Status: Granted - Kind: B2 - Application number: 17/077,579 - Filed: 2020-10-22 - Published: 2021-04-29 - Granted: 2024-06-18 - Earliest claimed: 2019-10-24 - Assignees: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. - Applicants: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. - Inventors: Maciej Cwiklinski - Web page: https://patentgrep.com/patent/US12015062B2 ## CPC - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H03F 1/42: Modifications of amplifiers to extend the bandwidth - H03F 3/195: in integrated circuits - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H10D 84/01: Manufacture or treatment - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/05: using Group III-V technology - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 84/82: of only field-effect components - H10D 86/01: Manufacture or treatment - H10D 86/03: wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS] - H03F 2200/39: Different band amplifiers are coupled in parallel to broadband the whole amplifying circuit - H03F 2200/451: the amplifier being a radio frequency amplifier - H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 89/10: Integrated device layouts - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H03F: AMPLIFIERS ## Abstract An integrated circuit is disclosed comprising at least one first field effect transistor, having at least one first source contact and at least one first drain contact and at least one first gate contact, and at least one second field effect transistor, having at least one second source contact and at least one second drain contact and at least one second gate contact, wherein the first drain contact is connected to the second drain contact, and the first source contact is coupled to the second gate contact, wherein the first source contact, the first drain contact, the first gate contact, the second source contact, the second drain contact and the second gate contact are implemented as structured metallization layers on a single substrate, and the first and second drain contacts share at least one single dedicated surface area on said substrate. ## Claims ### Claim 1 An fT-doubler amplifier integrated circuit having a high gain-bandwidth product comprising: at least one first field effect transistor of the fT-doubler amplifier integrated circuit, having at least one first source contact and at least one first drain contact and at least one first gate contact, and at least one second field effect transistor of the fT-doubler amplifier integrated circuit, having at least one second source contact and at least one second drain contact and at least one second gate contact, wherein the first drain contact is connected to the second drain contact, and the first source contact is coupled to the second gate contact, wherein the first source contact, the first drain contact, the first gate contact, the second source contact, the second drain contact and the second gate contact are implemented as structured metallization layers on a single substrate, the first and second drain contacts share at least one single dedicated surface area on said substrate, and the first source contact and the second gate contact share one single dedicated surface area on said substrate. ### Claim 2 (depends on 1) The fT-doubler amplifier integrated circuit according to claim 1, wherein said substrate comprises at least one material selected from the group consisting of Al2O3 and SiC and Si and a group-III-nitride and a III-V compound semiconductor and a II-VI compound semiconductor. ### Claim 3 (depends on 1) The fT-doubler amplifier integrated circuit according to claim 1, wherein the first and second drain contacts are configured as a signal output and the first gate contact is configured as a signal input. ### Claim 4 (depends on 1) The fT-doubler amplifier integrated circuit according to claim 1, comprising further a direct current path having a first end and a second end, wherein the first end is connected to the second gate contact and the second end is connected to a reference potential. ### Claim 5 (depends on 1) The fT-doubler amplifier integrated circuit according to claim 1, wherein the first and second drain contacts share two dedicated surface areas on said substrate, which are arranged on opposite sides of the surface area of the first source contact. ### Claim 6 (depends on 5) The fT-doubler amplifier integrated circuit according to claim 5, wherein at least two second source contacts are arranged adjacent to the surface areas of said first and second drain contacts and on the sides of the surface areas of the first and second drain contacts facing away from the first source contact. ### Claim 7 (depends on 4) The fT-doubler amplifier integrated circuit according to claim 4, wherein the direct current path comprises any of at least one resistor and/or at least one inductor. ### Claim 8 (depends on 1) The fT-doubler amplifier integrated circuit according to claim 1, comprising further at least one capacitor having two connectors being connected to the first source contact and the second gate contact, respectively. ### Claim 9 An fT-doubler amplifier integrated circuit, comprising at least one first field effect transistor of the fT-doubler amplifier integrated circuit, having at least one first source contact and at least one first drain contact and at least one first gate contact, and at least one second field effect transistor of the fT-doubler amplifier integrated circuit, having at least one second source contact and at least one second drain contact and at least one second gate contact, wherein the first drain contact is connected to the second drain contact, and the first source contact is coupled to the second gate contact, wherein the first source contact, the first drain contact, the first gate contact, the second source contact, the second drain contact and the second gate contact are implemented as structured metallization layers on a single substrate, and wherein the first and second drain contacts share at least one single dedicated surface area on said substrate, wherein the first and second drain contacts are configured as a single signal output and the first gate contact is configured as a signal input, wherein the first source contact and the second gate contact share one single dedicated surface area on said substrate, and wherein the first and second drain contacts share two dedicated surface areas on said substrate, which are arranged on opposite sides of the surface area of the first source contact. ### Claim 10 (depends on 9) The fT-doubler amplifier integrated circuit according to claim 9, comprising further a direct current path having a first end and a second end, wherein the first end is connected to the second gate contact and the second end is connected to a reference potential. ### Claim 11 (depends on 9) The fT-doubler amplifier integrated circuit according to claim 9, wherein at least two second source contacts are arranged adjacent to the surface areas of said first and second drain contacts and on the sides of the surface areas of the first and second drain contacts facing away from the first source contact. ### Claim 12 (depends on 9) The fT-doubler amplifier integrated circuit according to claim 9, comprising further at least one capacitor having two connectors being connected to the first source contact and the second gate contact, respectively. ### Claim 13 (depends on 9) The fT-doubler amplifier integrated circuit according to claim 9, wherein the first source contact and the second gate contact share one single dedicated surface area on said substrate. ### Claim 14 An electronic device comprising at least one fT-doubler amplifier integrated circuit, said fT-doubler amplifier integrated circuit comprising at least one first field effect transistor of the fT-doubler amplifier integrated circuit, having at least one first source contact and at least one first drain contact and at least one first gate contact, and at least one second field effect transistor of the fT-doubler amplifier integrated circuit, having at least one second source contact and at least one second drain contact and at least one second gate contact, wherein the first drain contact is connected to the second drain contact, and the first source contact is coupled to the second gate contact, wherein the first source contact, the first drain contact, the first gate contact, the second source contact, the second drain contact and the second gate contact are implemented as structured metallization layers on a single substrate, and wherein the first and second drain contacts share at least one single dedicated surface area on said substrate, and wherein the first and second drain contacts are configured as a single signal output and the first gate contact is configured as a signal input, and the first source contact and the second gate contact share one single dedicated surface area on said substrate. ### Claim 15 (depends on 14) The electronic device according to claim 14, comprising further a direct current path having a first end and a second end, wherein the first end is connected to the second gate contact and the second end is connected to a reference potential. ### Claim 16 (depends on 14) The electronic device according to claim 14, wherein the first and second drain contacts share two dedicated surface areas on said substrate, which are arranged on opposite sides of the surface area of the first source contact. ### Claim 17 (depends on 16) The electronic device according to claim 16, wherein at least two second source contacts are arranged adjacent to the surface areas of said first and second drain contacts and on the sides of the surface areas of the first and second drain contacts facing away from the first source contact. ### Claim 18 (depends on 1) The fT-doubler amplifier integrated circuit of claim 1, wherein the fT-doubler amplifier integrated circuit has a cutoff frequency that is at least 10% higher than a cutoff frequency of a comparable single field effect transistor in a common source topology. ### Claim 19 (depends on 9) The fT-doubler amplifier integrated circuit of claim 9, wherein the fT-doubler amplifier integrated circuit has a cutoff frequency that is at least 10% higher than a cutoff frequency of a comparable single field effect transistor in a common source topology. ### Claim 20 (depends on 14) The electronic device comprising the at least one fT-doubler amplifier integrated circuit of claim 14, wherein the fT-doubler amplifier integrated circuit has a cutoff frequency that is at least 10% higher than a cutoff frequency of a comparable single field effect transistor in a common source topology.