# US 12,015,060 B2 · Structure and formation method of semiconductor device with backside contact

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- Number: US 12,015,060 B2
- Document ID: US12015060B2
- Status: Granted
- Kind: B2
- Application number: 17/357,052
- Filed: 2021-06-24
- Published: 2022-12-29
- Granted: 2024-06-18
- Earliest claimed: 2021-06-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Feng-Ching Chu; Wei-Yang Lee; Chia-Pin Lin
- Web page: https://patentgrep.com/patent/US12015060B2

## CPC

- H10D 30/6729: {characterised by the electrodes}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6743: {Silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/364: {of IGFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/427: {Power or ground buses}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device structure and a formation method are provided. The semiconductor device structure includes a stack of channel structures and includes a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. The semiconductor device structure also includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. The second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. The semiconductor device structure further includes a dielectric fin stacked over an isolation structure. The dielectric fin is adjacent to the second epitaxial structure, and the isolation structure is adjacent to the backside conductive contact. The isolation structure has a first height, the dielectric fin has a second height, and the second height is greater than the first height.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a stack of channel structures;
a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures;
a gate stack wrapped around each of the channel structures;
a backside conductive contact connected to the second epitaxial structure, wherein the second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack;
a nitride layer extending along a sidewall of the backside conductive contact and a bottom of the gate stack; and
a dielectric fin stacked over an isolation structure, wherein the dielectric fin is adjacent to the second epitaxial structure, and the isolation structure is adjacent to the backside conductive contact.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising a metal-semiconductor compound layer between the backside conductive contact and the second epitaxial structure.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising a frontside conductive contact connected to the first epitaxial structure, wherein each of the channel structures is between the frontside conductive contact and the backside conductive contact.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the second epitaxial structure is wider than the backside conductive contact.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the second epitaxial structure is in direct contact with the dielectric fin.

### Claim 6 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the isolation structure has a first height, the dielectric fin has a second height, and a ratio of the second height to the first height is in a range from about 1.1 to about 1.8.

### Claim 7 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the isolation structure has a first height, the dielectric fin has a second height, the second epitaxial structure has a third height, and the third height is greater than the first height.

### Claim 8 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the isolation structure is in direct contact with a second sidewall of the backside conductive contact.

### Claim 9 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the isolation structure has a first height, the dielectric fin has a second height, and the second height is greater than the first height.

### Claim 10 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the second epitaxial structure continuously extends across top surfaces and bottom surfaces of the channel structures.

### Claim 11

A semiconductor device structure, comprising:
a stack of channel structures;
a first epitaxial structure and a second epitaxial structure sandwiching the channel structures;
a gate stack wrapped around the channel structures;
a backside conductive contact connected to the second epitaxial structure, wherein the backside conductive contact is below a bottom surface of the second epitaxial structure; and
a dielectric fin stacked over an isolation structure, wherein the dielectric fin is adjacent to the second epitaxial structure, the isolation structure is adjacent to the backside conductive contact, the isolation structure has a first height, the dielectric fin has a second height, and a ratio of the second height to the first height is in a range from about 0.75 to about 1.8.

### Claim 12 (depends on 11)

The semiconductor device structure as claimed in claim 11, wherein the ratio of the second height to the first height is in a range from about 1 to about 1.7.

### Claim 13 (depends on 11)

The semiconductor device structure as claimed in claim 11, wherein the second epitaxial structure has a third height, and the third height is greater than the first height.

### Claim 14 (depends on 11)

The semiconductor device structure as claimed in claim 11, wherein the backside conductive contact is in direct contact with the isolation structure.

### Claim 15 (depends on 14)

The semiconductor device structure as claimed in claim 14, wherein the isolation structure is in direct contact with the dielectric fin.

### Claim 16

A method for forming a semiconductor device structure, comprising:
forming a fin structure over a semiconductor substrate, wherein the fin structure has a plurality of sacrificial layers and a plurality of semiconductor layers laid out alternately;
surrounding a lower portion of the fin structure with an isolation structure, wherein a protruding portion of the fin structure above a top of the isolation structure has a first height that is greater than a second height of the isolation structure;
forming a first epitaxial structure and a second epitaxial structure sandwiching the fin structure;
removing the sacrificial layers to release a plurality of semiconductor nanostructures made of remaining portions of the semiconductor layers;
forming a gate stack to wrap around the semiconductor nanostructures;
removing a part of the lower portion of the fin structure to form an opening, wherein the opening is below the first epitaxial structure;
forming a dielectric filling in the opening; and
forming a backside conductive contact connected to the second epitaxial structure, wherein the backside conductive contact is adjacent to the isolation structure.

### Claim 17 (depends on 16)

The method for forming a semiconductor device structure as claimed in claim 16, further comprising:
forming a dummy epitaxial structure, wherein the dummy epitaxial structure is between the second epitaxial structure and the semiconductor substrate, and the dummy epitaxial structure is surrounded by the isolation structure; and
removing the dummy epitaxial structure to expose the second epitaxial structure after the dielectric filling is formed.

### Claim 18 (depends on 17)

The method for forming a semiconductor device structure as claimed in claim 17, further comprising thinning the semiconductor substrate to expose the isolation structure, the dummy epitaxial structure, and the lower portion of the fin structure before the opening is formed.

### Claim 19 (depends on 16)

The method for forming a semiconductor device structure as claimed in claim 16, further comprising:
forming a dielectric fin over the isolation structure, wherein the dielectric fin has a third height, and the third height is greater than the second height of the isolation structure.

### Claim 20 (depends on 19)

The method for forming a semiconductor device structure as claimed in claim 19, wherein a ratio of the third height to the second height is in a range from about 1.1 to about 1.8.