# US 12,015,057 B2 · Carbon, nitrogen and/or fluorine co-implants for low resistance transistors

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- Number: US 12,015,057 B2
- Document ID: US12015057B2
- Status: Granted
- Kind: B2
- Application number: 17/156,612
- Filed: 2021-01-24
- Published: 2022-06-30
- Granted: 2024-06-18
- Earliest claimed: 2020-12-31
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Mahalingam Nandakumar; Alexei Sadovnikov; Henry Litzmann Edwards; Jarvis Benjamin Jacobs
- Web page: https://patentgrep.com/patent/US12015057B2

## CPC

- H10D 62/80: characterised by the materials
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.

## Claims

### Claim 1

A semiconductor device including a drain extended metal oxide semiconductor field effect transistor (MOSFET), comprising:
a source region and a drain region each having a first conductivity type spaced apart along a surface of a semiconductor material having the first conductivity type and a top surface;
a gate electrode over the top surface of the semiconductor material between the source region and the drain region;
a body region having an opposite second conductivity type extending from the source region toward the drain region under the gate electrode;
a drift region having the first conductivity type extending from the body region toward the drain region; and
a diffusion suppression implant region overlapping the body region, the diffusion suppression implant region comprising at least one of carbon, nitrogen, and fluorine, the drain region and the drift region being free of carbon, nitrogen and fluorine.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the diffusion suppression implant region includes at least one of indium and germanium.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the diffusion suppression implant region includes carbon and nitrogen.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the body region includes a shallow n-type well that extends front the source region into the body region.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the drain region has a first dopant concentration and the drift region has a second drain region having a second dopant concentration no greater than ½ the first dopant concentration.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a field relief dielectric layer and a gate dielectric layer between the gate electrode and the surface of the semiconductor material, the gate dielectric layer extending from the field relief dielectric layer toward the source region and overlapping the diffusion suppression implant region.

### Claim 9

A semiconductor device including a drain-extended metal oxide semiconductor field effect transistor (MOSFET), comprising:
a source region and a drain region spaced apart in a semiconductor material, each having a first conductivity type;
a drain drift region extending from the drain region toward the source region and having the first conductivity type; and
a body region extending from the source region toward the drain drift region and having an opposite second conductivity type, the body region including a diffusion suppression dopant including at least one of implanted carbon and nitrogen and fluorine, and the drain drift region being free of carbon, nitrogen and fluorine.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the body region includes a well region having the second conductivity type, and the diffusion suppression dopant is located within the well region.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the well region is a first well region located within a second well region having the second conductivity type, the second well region extending further into the semiconductor material than the first well region.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the first conductivity type is p-type and the second conductivity type is n-type.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the diffusion suppression dopant includes each of carbon and nitrogen and fluorine.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the body region includes at least one of indium and germanium.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein a well region having the first conductivity type overlaps the body region and the source region and extends past the source region toward the drain drift region.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein the semiconductor material is a p-type epitaxial layer over a silicon substrate.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising an n-type buried layer between the silicon substrate and the epitaxial layer.