# US 12,015,056 B2 · Field effect transistor with controllable resistance

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- Number: US 12,015,056 B2
- Document ID: US12015056B2
- Status: Granted
- Kind: B2
- Application number: 18/306,359
- Filed: 2023-04-25
- Published: 2023-08-24
- Granted: 2024-06-18
- Earliest claimed: 2017-12-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Yulong Li; Paul M. Solomon; Siyuranga Koswatta
- Web page: https://patentgrep.com/patent/US12015056B2

## CPC

- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 41/30: characterised by the memory core region
- H10B 51/30: characterised by the memory core region
- H10B 63/00: Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10D 12/211: {Gated diodes}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0318: {of vertical TFTs}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/801: {FETs having heterojunction gate electrodes}
- H10D 48/366: {Multistable devices; Devices having two or more distinct operating states}
- H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects}
- H10D 62/114: {PN junction isolations}
- H10D 62/17: Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/689: {having ferroelectric layers}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

## Claims

### Claim 1

A semiconductor device comprising:
a source terminal;
a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;
an energy barrier adjacent to the source terminal and the channel region;
a conductive gate stack formed over the channel region, the conductive gate stack including;
a first gate dielectric layer on the channel region;
a second gate dielectric layer on the first gate dielectric layer;
a charge storage layer between the first gate dielectric layer and the second gate dielectric layer,
wherein the semiconductor device is configured to store a connection weight corresponding to a crosspoint device.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a capacitor configured to store a charge indicative of the connection weight.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the channel region includes a channel having a first amount of dopants and the energy barrier has a second amount of dopants greater than the first amount of dopants of the channel.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the energy barrier and the channel are doped with n-type dopants and the source terminal and the drain terminal are doped with p-type dopants.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the energy barrier has a size smaller than each of the source terminal and the channel.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the gate stack includes a pair of opposing spacers, wherein at least one of the spacers is on an upper surface of the energy barrier.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the charge storage layer comprises polysilicon.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the gate stack includes a conductive material layer on the second gate dielectric layer.

### Claim 9

A semiconductor device comprising:
a source terminal;
a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;
an energy barrier adjacent to the source terminal and the channel region; and
a conductive gate stack formed over the channel region, the conductive gate stack including:
at least one gate dielectric layer on the channel region; and
a gate electrode on the at least one gate dielectric layer;
a capacitor connected directly to the gate electrode and configured to store a charge indicative of a connection weight corresponding to a crosspoint device.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the capacitor includes a first terminal connected directly to the gate electrode and an opposing second terminal connected directly to a ground potential.