# US 12,015,055 B2 · Doping for semiconductor device with conductive feature

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,015,055 B2
- Document ID: US12015055B2
- Status: Granted
- Kind: B2
- Application number: 18/350,838
- Filed: 2023-07-12
- Published: 2023-11-02
- Granted: 2024-06-18
- Earliest claimed: 2017-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Su-Hao Liu; Huicheng Chang; Chia-Cheng Chen; Liang-Yin Chen; Kuo-Ju Chen; Chun-Hung Wu; Chang-Miao Liu; Huai-Tei Yang; Lun-Kuang Tan; Wei-Ming You
- Web page: https://patentgrep.com/patent/US12015055B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/834: further characterised by the dopants
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3438: {Doping during depositing}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

## Claims

### Claim 1

A method comprising:
forming a source/drain region over a substrate, the source/drain region being doped with p-type dopants;
implanting gallium into the source/drain region, the gallium having a platform dopant region and a tailing dopant region, wherein the platform dopant region extends from a surface of the source/drain region to a first depth in the source/drain region, wherein a gallium concentration in the tailing dopant region decreases with a gradient as the tailing dopant region extends away from the platform dopant region, wherein implanting gallium into the source/drain region amorphizes at least a portion of the source/drain region;
after implanting gallium into the source/drain region, forming a dielectric layer over the source/drain region, the dielectric layer having an opening over the source/drain region; and
forming a conductive feature in the opening.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first depth is about 8 nm.

### Claim 3 (depends on 1)

The method of claim 1, further comprising amorphizing at least a portion of the source/drain region using a dopant prior to implanting gallium, wherein the dopant is different from gallium.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first depth is about 12 nm.

### Claim 5 (depends on 3)

The method of claim 3, wherein the dopant is germanium and the source/drain region comprises silicon germanium.

### Claim 6 (depends on 1)

The method of claim 1, wherein the dielectric layer extends under the source/drain region.

### Claim 7 (depends on 1)

The method of claim 1, wherein the platform dopant region has a concentration of gallium in a range between 1021 cm−3 and 1022 cm−3.

### Claim 8

A method comprising:
forming a first source/drain region in a semiconductor region;
implanting a first dopant into the first source/drain region;
annealing the first source/drain region, wherein after annealing a concentration profile of the first dopant in the first source/drain region has a platform dopant region and a tailing dopant region, wherein a first concentration of the first dopant in the platform dopant region is steady, wherein a second concentration of the first dopant in the tailing dopant region decreases as the tailing dopant region extends away from the platform dopant region;
after annealing the first source/drain region, forming a dielectric layer over the first source/drain region;
patterning the dielectric layer to form an opening, the opening exposing an exposed portion of the first source/drain region; and
forming a contact to the platform dopant region.

### Claim 9 (depends on 8)

The method of claim 8, wherein, after annealing, the platform dopant region has a depth of about 8 nm.

### Claim 10 (depends on 8)

The method of claim 8, wherein implanting the first dopant amorphizes at least a portion of the first source/drain region.

### Claim 11 (depends on 8)

The method of claim 8, wherein, after patterning, the platform dopant region extends to a depth of 3 nm from a bottom of the opening.

### Claim 12 (depends on 8)

The method of claim 8, wherein, after patterning, the platform dopant region extends to a depth of 5 nm from a bottom of the opening.

### Claim 13 (depends on 8)

The method of claim 8, further comprising, prior to implanting the first dopant, implanting a second dopant, wherein implanting the second dopant amorphizes a portion of the first source/drain region.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second dopant comprises germanium.

### Claim 15

A method comprising:
forming a first source/drain region in a semiconductor region;
amorphizing a portion of the first source/drain region to form an amorphous region;
implanting a first dopant into the amorphous region, wherein the first dopant is a dopant of the first conductivity type; and
recrystallizing the amorphous region, wherein after recrystallizing, a dopant profile of the first dopant comprises a platform dopant region and a tailing dopant region, the platform dopant region having an even doping profile of the first dopant to a first depth, the tailing dopant region having a decreasing concentration of the first dopant as the tailing dopant region extends away from the platform dopant region; and
after recrystallizing, forming a dielectric layer over the first source/drain region.

### Claim 16 (depends on 15)

The method of claim 15, wherein amorphizing is performed by implanting germanium.

### Claim 17 (depends on 15)

The method of claim 15, further comprising forming a silicide region on a surface of the platform dopant region.

### Claim 18 (depends on 17)

The method of claim 17, wherein a depth of the silicide region is less than a depth of the platform dopant region.

### Claim 19 (depends on 15)

The method of claim 15, wherein the dielectric layer extends under the first source/drain region.

### Claim 20 (depends on 15)

The method of claim 15, wherein platform dopant region has a dopant concentration that ranges between 1021 cm−3 to about 1022 cm−3.