# US 12,015,054 B2 · False collectors and guard rings for semiconductor devices

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- Number: US 12,015,054 B2
- Document ID: US12015054B2
- Status: Granted
- Kind: B2
- Application number: 17/710,320
- Filed: 2022-03-31
- Published: 2023-10-05
- Granted: 2024-06-18
- Earliest claimed: 2022-03-31
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Alexei Sadovnikov; Guruvayurappan S. Mathur
- Web page: https://patentgrep.com/patent/US12015054B2

## CPC

- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 10/00: Bipolar junction transistors [BJT]
- H10D 10/01: Manufacture or treatment
- H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)}
- H10D 10/60: Lateral BJTs
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

## Claims

### Claim 1

An integrated circuit comprising:
active semiconductor devices in a substrate; and
a lateral isolation region configured to isolate a given active semiconductor device from neighboring active semiconductor devices, the lateral isolation region comprising:
first and second doped regions having a first conductivity type located adjacent to a surface of the lateral isolation region, the second doped region located laterally further away from the given active semiconductor device than the first doped region;
a third doped region located laterally between the first and second doped regions and adjacent to the surface of the lateral isolation region, the third doped region having a second conductivity type opposite of the first conductivity type, the first, third, and second doped regions respectively forming a collector, a base, and an emitter of a parasitic bipolar junction transistor of the lateral isolation region; and
first and second false collector regions of the first conductivity type adjacent to the surface of the lateral isolation region, the first false collector region located laterally between the collector and the base, and the second false collector region located laterally between the base and the emitter.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, further comprising:
first and second guard regions located adjacent to the surface of the lateral isolation region and having the second conductivity type, the first guard region located laterally between the first doped region and the first false collector region, and the second guard region located laterally between the second false collector region and the second doped region.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein the first and second guard regions are doped with boron.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein dopants in the first and second guard regions have a concentration of between about 1×1016 ions/cm3 and about 1×1018 ions/cm3.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the first and second false collector regions are doped with arsenic or phosphorus.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein dopants in the first and second false collector regions have a concentration of between about 1×1019 ions/cm3 and about 1×1020 ions/cm3.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein the base is coupled to a voltage source, or to a ground, through a high-impedance circuit, or the base is electrically floating.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the lateral isolation region encircles the given active semiconductor device.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, wherein the lateral isolation region partially surrounds the given active semiconductor device.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, further comprising:
a field oxide region located laterally between the collector and the base, wherein the field oxide region includes a portion overlapping with the collector.

### Claim 11 (depends on 1)

The integrated circuit of claim 1, further comprising:
a field oxide region located laterally between the base and the emitter, wherein the field oxide region includes a portion overlapping with the emitter.

### Claim 12 (depends on 1)

The integrated circuit of claim 1, wherein the first and second false collector regions are shorted to the base.

### Claim 13

A semiconductor device, comprising:
a substrate including a semiconductor component; and
a lateral isolation region that at least partially surrounds the semiconductor component, the lateral isolation region including:
first and second doped regions having a first conductivity type and vertically extended from a surface of the substrate, wherein the second doped region is located laterally further away from the semiconductor component than the first doped region;
a third doped region located having a second conductivity type opposite of the first conductivity type and vertically extended from the surface, wherein the third doped region is located laterally between the first and second doped regions, and wherein the first, third, and second doped regions respectively forming a collector, a base, and an emitter of a parasitic bipolar junction transistor of the lateral isolation region; and
a false collector region of the first conductivity type vertically extended from the surface, wherein the false collector region is located laterally between the collector and the base.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein in the false collector region is a first false collector region, and the lateral isolation region further comprises:
a second false collector region of the first conductivity type and vertically extended from the surface, wherein the second false collector region is located laterally between the base and the emitter.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising:
a guard region of the second conductivity type and vertically extended from the surface, wherein the guard region is located laterally between the collector and the false collector region.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the guard region is a first guard region, and the lateral isolation region further comprises:
a second guard region of the second conductivity type and vertically extended from the surface, wherein the second guard region is located laterally between the second false collector region and the emitter.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein the false collector region is shorted to the base.

### Claim 18 (depends on 13)

The semiconductor device of claim 13, further comprising:
a field oxide region located laterally between the collector and the base, wherein the field oxide region includes a portion overlapping with the collector.

### Claim 19 (depends on 13)

The semiconductor device of claim 13, further comprising:
a field oxide region located laterally between the base and the emitter, wherein the field oxide region includes a portion overlapping with the emitter.

### Claim 20 (depends on 13)

The semiconductor device of claim 13, further comprising:
a buried doped layer in the substrate, the buried doped layer having the second conductivity type and located underneath the collector and the base, wherein the base is coupled to the buried doped layer.

### Claim 21 (depends on 13)

The semiconductor device of claim 13, further comprising:
a buried doped layer in the substrate, the buried doped layer having the first conductivity type and located underneath the collector, the base, and the emitter, wherein the emitter is coupled to the buried doped layer.

### Claim 22 (depends on 13)

The semiconductor device of claim 13, wherein the semiconductor component includes a diode, a lateral-diffused metal-oxide semiconductor field effect transistor, or a bipolar junction transistor.