# US 12,015,049 B2 · Ring structure for film resistor

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- Number: US 12,015,049 B2
- Document ID: US12015049B2
- Status: Granted
- Kind: B2
- Application number: 17/579,129
- Filed: 2022-01-19
- Published: 2022-05-12
- Granted: 2024-06-18
- Earliest claimed: 2019-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Tsung Kuo; Jiech-Fun Lu
- Web page: https://patentgrep.com/patent/US12015049B2

## CPC

- H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes depositing a resistive layer over a substrate. A conductive structure is formed over the resistive layer. A first etch process is performed on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer. The resistor segment is laterally separated from the peripheral region of the resistive layer. The peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.

## Claims

### Claim 1

A method for forming an integrated chip, comprising:
depositing a resistive layer over a substrate;
forming a conductive structure over the resistive layer; and
performing a first etch process on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer, wherein the resistor segment is laterally separated from the peripheral region of the resistive layer, and wherein the peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming an isolation structure around the outer perimeter of the resistor segment.

### Claim 3 (depends on 2)

The method of claim 2, wherein the isolation structure continuously extends from a first point above the conductive structure to a second point below a bottom surface of the resistive layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first etch process defines an opening around the resistor segment of the resistive layer, and wherein forming the isolation structure comprises:
forming a liner layer within the opening; and
forming a conductive body within the opening such that the liner layer is disposed along opposing sidewalls of the conductive body.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first etch process removes at least a portion of the conductive structure.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a first dielectric layer between the substrate and the resistive layer;
forming a conductive wire within the first dielectric layer; and
wherein after performing the first etch process the conductive wire directly underlies at least a portion of the peripheral region of the resistive layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first etch process exposes an upper surface of the conductive wire.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the conductive structure comprises:
depositing a conductive layer and a dielectric layer on a top surface of the resistive layer;
performing a second etch process on the dielectric layer and the conductive layer to reduce a thickness of the conductive layer and to define a dielectric structure; and
performing a third etch process on the conductive layer to define the conductive structure.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second etch process comprises a dry etch process and the third etch process comprises a wet etch process.

### Claim 10

A method for forming a semiconductor structure, comprising:
depositing a lower dielectric layer over a substrate;
depositing a resistor layer over the lower dielectric layer; and
forming an isolation structure over the lower dielectric layer, wherein the isolation structure extends through the resistor layer and envelopes a perimeter of a resistor segment of the resistor layer, wherein forming the isolation structure comprises:
patterning the resistor layer to define an opening that surrounds the resistor segment;
depositing a dielectric liner over the resistor layer, wherein the dielectric liner lines the opening; and
forming a conductive body within the opening, wherein the dielectric liner separates the conductive body from the resistor layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the isolation structure contacts a first sidewall of the resistor segment and a second sidewall of the resistor segment, wherein the first sidewall is perpendicular to the second sidewall.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
performing an etch back process on the dielectric liner to remove the dielectric liner from an upper surface of the lower dielectric layer.

### Claim 13 (depends on 10)

The method of claim 10, wherein a bottom surface of the conductive body directly contacts an upper surface of the lower dielectric layer.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
forming contact structures over the resistor segment of the resistor layer; and
forming conductive vias over the contact structures, wherein the conductive vias are formed concurrently with the isolation structure.

### Claim 15 (depends on 14)

The method of claim 14, wherein bottom surfaces of the contact structures directly contact a top surface of the resistor segment of the resistor layer.

### Claim 16 (depends on 10)

The method of claim 10, further comprising:
forming a pair of conductive structures on opposing sides of the resistor segment, wherein the conductive structures are spaced between inner sidewalls of the isolation structure.

### Claim 17

A method of forming an integrated chip, comprising:
depositing a resistive layer over a substrate, wherein the resistive layer comprises a first material;
forming a conductive structure over the resistive layer, wherein the conductive structure comprises a second material different than the first material;
forming an inter-level dielectric (ILD) structure over the conductive structure;
patterning the ILD structure and the resistive layer to define a plurality of via openings and a ring structure opening, such that the ring structure opening laterally encloses a resistor segment of the resistive layer, wherein the ring structure opening extends from an upper surface of the ILD structure to a point below the resistive layer;
forming a plurality of conductive vias in the plurality of via openings; and
forming a ring structure within the ring structure opening.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming the plurality of conductive vias and the ring structure comprises:
forming a dielectric liner that at least partially lines the plurality of via openings and the ring structure opening;
depositing a conductive material in the plurality of via openings and the ring structure opening; and
performing a planarization process into the conductive material, thereby defining a conductive body in the ring structure opening and the plurality of conductive vias in the plurality of via openings, wherein the ring structure comprises the dielectric liner and the conductive body such that the dielectric liner separates the conductive body from the resistor segment of the resistive layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the conductive vias and the ring structure are formed concurrently.

### Claim 20 (depends on 17)

The method of claim 17, wherein a process for forming the conductive structure includes:
depositing a conductive layer over the resistive layer;
depositing a dielectric layer over the conductive layer;
performing a dry etch process on the dielectric layer and the conductive layer, thereby defining a dielectric structure over the conductive layer; and
performing a wet etch process on the conductive layer, thereby defining the conductive structure such that a width of the dielectric structure is greater than a width of the conductive structure.