# US 12,015,033 B2 · Array substrate and method for manufacturing the same, display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,033 B2 - Document ID: US12015033B2 - Status: Granted - Kind: B2 - Application number: 17/435,337 - Filed: 2020-12-30 - Published: 2023-06-08 - Granted: 2024-06-18 - Earliest claimed: 2020-03-25 - Assignees: Beijing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Beijing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Wei Chen; Weixiong Chen; Xin Li; Yong Song - Web page: https://patentgrep.com/patent/US12015033B2 ## CPC - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G09G 3/3622: {using a passive matrix (G09G3/3674 - G09G3/3696 take precedence)} - H10D 86/021: {of multiple TFTs} - H10D 86/441: {Interconnections, e.g. scanning lines} - G02F 1/133331: {Cover glasses} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0281: Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure - G09G 2310/0283: Arrangement of drivers for different directions of scanning - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An array substrate includes a base, a first conductive layer disposed at a side of the base, an insulating layer disposed at a side of the first conductive layer away from the base, and a second conductive layer disposed at a side of the insulating layer away from the first conductive layer. The insulating layer is provided with a first via hole exposing the first electrode of the first transistor and a second via hole exposing the first electrode of the second transistor. The second conductive layer includes a first conductive connection portion, and the first conductive connection portion connects the first electrode of the first transistor and the first electrode of the second transistor through the first via hole and the second via hole. ## Claims ### Claim 1 An array substrate having an active area and a non-active area adjacent to the active area; the array substrate comprising: a base; a first conductive layer disposed at a side of the base, a portion of the first conductive layer located in the non-active area including at least a first electrode of a first transistor and a first electrode of a second transistor, there being a distance between the first electrode of the first transistor and the first electrode of the second transistor, and the first transistor and the second transistor being at least a part of a shift register of a same stage in a gate driving circuit; an insulating layer disposed at a side of the first conductive layer away from the base, and the insulating layer being provided with a first via hole exposing the first electrode of the first transistor and a second via hole exposing the first electrode of the second transistor; and a second conductive layer disposed at a side of the insulating layer away from the first conductive layer, the second conductive layer including a first conductive connection portion, and the first conductive connection portion connecting the first electrode of the first transistor and the first electrode of the second transistor through the first via hole and the second via hole. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein the portion of the first conductive layer located in the non-active area further includes: an output signal line, and the output signal line having a first end away from the active area and a second end proximate to the active area; the first end of the output signal line being coupled to a scanning signal output terminal of the shift register; and a common electrode block, and the common electrode block being configured to transmit a common voltage signal; a distance between the common electrode block and the output signal line being in a range of about 22 μm to about 42 μm. ### Claim 3 (depends on 2) The array substrate according to claim 2, wherein the first conductive layer further includes: a common voltage line, the common voltage line extending from the active area to the non-active area, and an end portion of the common voltage line located in the non-active area being connected to the common electrode block; and a gate line, the gate line extending from the active area to the non-active area, and an end portion of the gate line located in the non-active area being coupled to the second end of the output signal line. ### Claim 4 (depends on 3) The array substrate according to claim 3, wherein the insulating layer is provided with a third via hole exposing the second end of the output signal line and a fourth via hole exposing the end portion of the gate line located in the non-active area; and the second conductive layer further includes: a second conductive connection portion, and the second conductive connection portion connecting the end portion of the gate line located in the non-active area and the second end of the output signal line through the third via hole and the fourth via hole, so that the end portion of the gate line located in the non-active area is coupled to the second end of the output signal line. ### Claim 5 (depends on 3) The array substrate according to claim 3, wherein a distance between the end portion of the gate line located in the non-active area and the second end of the output signal line is in a range of about 5 μm to about 15 μm; or a distance between any two of the first end of the output signal line, the first electrode of the first transistor and the first electrode of the second transistor is in a range of about 5 μm to about 15 μm; or a distance between the end portion of the gate line located in the non-active area and the second end of the output signal line is in a range of about 5 μm to about 15 μm, and a distance between any two of the first end of the output signal line, the first electrode of the first transistor and the first electrode of the second transistor is in a range of about 5 μm to about 15 μm. ### Claim 6 (depends on 2) The array substrate according to claim 2, wherein a dimension of the common electrode block in a direction parallel to an edge of the active area is in a range of about 60 μm to about 80 μm. ### Claim 7 (depends on 1) The array substrate according to claim 1, wherein a portion of the second conductive layer located in the non-active area further includes: an output signal line, and the output signal line having a first end away from the active area and a second end proximate to the active area; the first end of the output signal line being coupled to a scanning signal output terminal of the shift register. ### Claim 8 (depends on 7) The array substrate according to claim 7, wherein the first conductive layer further includes: a gate line, and the gate line extending from the active area to the non-active area; and the insulating layer is provided with a fifth via hole exposing an end portion of the gate line located in the non-active area, and the second end of the output signal line being connected to an end portion of the gate line located in the non-active area through the fifth via hole. ### Claim 9 (depends on 2) The array substrate according to claim 2, wherein the shift register includes: a capacitor disposed on the base, a first electrode of the capacitor being coupled to the scanning signal output terminal of the shift register, and a second electrode of the capacitor being coupled to the first conductive connection portion. ### Claim 10 (depends on 9) The array substrate according to claim 9, wherein one of the first electrode of the capacitor and the second electrode of the capacitor is located in the first conductive layer, and another is located in the second conductive layer. ### Claim 11 (depends on 1) The array substrate according to claim 1, wherein the portion of the first conductive layer located in the non-active area further includes: a second electrode of the first transistor; a second electrode of the second transistor; a forward scan line, the forward scan line being disposed around the active area, and the forward scan line being disposed at a side of the gate driving circuit away from the active area; and a reverse scan line, the reverse scan line being disposed around the active area, and the reverse scan line being disposed at the side of the gate driving circuit away from the active area; wherein the second electrode of the first transistor is connected to the forward scan line, or the second electrode of the second transistor is connected to the reverse scan line, or the second electrode of the first transistor is connected to the forward scan line and the second electrode of the second transistor is connected to the reverse scan line. ### Claim 12 A method for manufacturing an array substrate, the array substrate having an active area and a non-active area adjacent to the active area, and the method comprising: providing a base; forming a first conductive layer at a side of the base, a portion of the first conductive layer located in the non-active area including at least a first electrode of a first transistor and a first electrode of a second transistor, there being a distance between the first electrode of the first transistor and the first electrode of the second transistor, and the first transistor and the second transistor being at least a part of a shift register of a same stage in a gate driving circuit; forming an insulating layer at a side of the first conductive layer away from the base; etching the insulating layer to form a first via hole exposing the first electrode of the first transistor and a second via hole exposing the first electrode of the second transistor; and forming a second conductive layer at a side of the insulating layer away from the first conductive layer, the second conductive layer including a first conductive connection portion, and the first conductive connection portion connecting the first electrode of the first transistor and the first electrode of the second transistor through the first via hole and the second via hole. ### Claim 13 (depends on 1) A display panel, comprising: the array substrate according to claim 1; and a transparent cover plate disposed at a side of the array substrate. ### Claim 14 (depends on 13) A display device, comprising: the display panel according to claim 13; and a power module, the power module being coupled to the array substrate in the display panel, and the power module being configured to supply power to the array substrate. ### Claim 15 (depends on 4) The array substrate according to claim 4, wherein a distance between the end portion of the gate line located in the non-active area and the second end of the output signal line is in a range of about 5 μm to about 15 μm; or a distance between any two of the first end of the output signal line, the first electrode of the first transistor and the first electrode of the second transistor is in a range of about 5 μm to about 15 μm; or a distance between the end portion of the gate line located in the non-active area and the second end of the output signal line is in a range of about 5 μm to about 15 μm, and a distance between any two of the first end of the output signal line, the first electrode of the first transistor and the first electrode of the second transistor is in a range of about 5 μm to about 15 μm. ### Claim 16 (depends on 7) The array substrate according to claim 7, wherein the shift register includes: a capacitor disposed on the base, a first electrode of the capacitor being coupled to the scanning signal output terminal of the shift register, and a second electrode of the capacitor being coupled to the first conductive connection portion. ### Claim 17 (depends on 16) The array substrate according to claim 16, wherein one of the first electrode of the capacitor and the second electrode of the capacitor is located in the first conductive layer, and another is located in the second conductive layer.