# US 12,015,031 B2 · Semiconductor device and method

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- Number: US 12,015,031 B2
- Document ID: US12015031B2
- Status: Granted
- Kind: B2
- Application number: 17/961,949
- Filed: 2022-10-07
- Published: 2023-02-02
- Granted: 2024-06-18
- Earliest claimed: 2021-01-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wan-Yi Kao; Szu-Ping Lee; Che-Hao Chang; Chun-Heng Chen; Yung-Cheng Lu; Chi On Chui
- Web page: https://patentgrep.com/patent/US12015031B2

## CPC

- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/853: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

## Claims

### Claim 1

A method comprising:
forming a first fin and a second fin extending from a semiconductor substrate;
depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration;
depositing a fill material on the liner layer, the fill material formed of silicon;
annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and
recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

### Claim 2 (depends on 1)

The method of claim 1, wherein the annealing the liner layer and the fill material decreases a thickness of the liner layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the thickness of the liner layer before the annealing is in a range of 15 Å to 50 Å, and the thickness of the liner layer after the annealing is in a range of 1 Å to 10 Å.

### Claim 4 (depends on 1)

The method of claim 1, wherein the depositing the liner layer comprises:
placing the semiconductor substrate in a deposition chamber;
performing an atomic layer deposition cycle comprising:
introducing hexachlorodisilane into the deposition chamber;
purging the hexachlorodisilane from the deposition chamber;
introducing oxygen into the deposition chamber;
purging the oxygen from the deposition chamber;
introducing ammonia into the deposition chamber; and
purging the ammonia from the deposition chamber; and
repeating the atomic layer deposition cycle.

### Claim 5 (depends on 4)

The method of claim 4, wherein the hexachlorodisilane is kept in the deposition chamber for a duration in a range of 5 seconds to 120 seconds, the oxygen is kept in the deposition chamber for a duration in a range of 5 seconds to wo seconds, the ammonia is kept in the deposition chamber for a duration in a range of 5 seconds to wo seconds, and the atomic layer deposition cycle is repeated from 5 to 100 times.

### Claim 6 (depends on 4)

The method of claim 4, wherein the hexachlorodisilane, the oxygen, and the ammonia are each introduced at a temperature in a range of 450° C. to 700° C.

### Claim 7 (depends on 1)

The method of claim 1, wherein the annealing the liner layer and the fill material comprises:
performing a wet anneal process at a temperature in a range of 400° C. to 750° C. and for a duration in a range of 1 hour to 5 hours.

### Claim 8 (depends on 7)

The method of claim 7, wherein the wet anneal process is performed with steam produced by in-situ steam generation.

### Claim 9 (depends on 1)

The method of claim 1, wherein after the annealing the liner layer and the fill material, the nitrogen concentration of the liner layer is greater than zero.

### Claim 10

A method comprising:
forming a first fin and a second fin extending from a semiconductor substrate;
forming a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate with an atomic layer deposition process, the liner layer formed of silicon oxynitride having a nitrogen concentration;
forming a fill material on the liner layer with a flowable chemical vapor deposition process, the flowable chemical vapor deposition process comprising:
depositing a semiconductor layer on the liner layer, the semiconductor layer formed of silicon; and
annealing the semiconductor layer and the liner layer, the annealing converting the semiconductor layer and an upper portion of the liner layer to silicon oxide, the annealing decreasing the nitrogen concentration of a lower portion of the liner layer; and
recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

### Claim 11 (depends on 10)

The method of claim 10, wherein the atomic layer deposition process comprises:
placing the semiconductor substrate in a deposition chamber;
performing an atomic layer deposition cycle comprising:
introducing hexachlorodisilane into the deposition chamber;
purging the hexachlorodisilane from the deposition chamber;
introducing oxygen into the deposition chamber;
purging the oxygen from the deposition chamber;
introducing ammonia into the deposition chamber; and
purging the ammonia from the deposition chamber; and
repeating the atomic layer deposition cycle.

### Claim 12 (depends on 10)

The method of claim 10, wherein the recessing the liner layer and the fill material comprises:
etching the liner layer and the fill material with an etching process, wherein annealing the liner layer decreases an etching selectivity between the liner layer and the fill material relative the etching process.

### Claim 13 (depends on 10)

The method of claim 10, wherein no oxidation of the first fin or the second fin occurs when annealing the semiconductor layer and the liner layer.

### Claim 14 (depends on 10)

The method of claim 10, wherein after the annealing the semiconductor layer and the liner layer, the nitrogen concentration of the lower portion of the liner layer is greater than the nitrogen concentration of the upper portion of the liner layer.

### Claim 15

A method comprising:
forming a first fin and a second fin extending from a semiconductor substrate;
depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate with an atomic layer deposition process;
depositing a fill material on the liner layer with a flowable chemical vapor deposition process, the flowable chemical vapor deposition process comprising an anneal process, the anneal process decreasing an etching selectivity between the liner layer and the fill material relative an etching process;
forming an isolation region between the first fin and the second fin by etching the liner layer and the fill material with the etching process; and
forming a gate structure on a top surface of the isolation region, the first sidewall of the first fin, and the second sidewall of the second fin.

### Claim 16 (depends on 15)

The method of claim 15, wherein after the etching the liner layer and the fill material, top surfaces of the liner layer and the fill material are coplanar.

### Claim 17 (depends on 15)

The method of claim 15, wherein the etching process removes the liner layer and the fill material at the same rate.

### Claim 18 (depends on 15)

The method of claim 15, wherein the flowable chemical vapor deposition process comprises:
depositing a semiconductor material with a chemical vapor deposition process; and
converting the semiconductor material to a dielectric material by annealing the semiconductor material.

### Claim 19 (depends on 18)

The method of claim 18, wherein no oxidation of the first fin or the second fin occurs during the annealing the semiconductor material.

### Claim 20 (depends on 15)

The method of claim 15, wherein the anneal process decreases a nitrogen concentration of the liner layer.