# US 12,015,023 B2 · Integrated circuit package and method of forming same

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- Number: US 12,015,023 B2
- Document ID: US12015023B2
- Status: Granted
- Kind: B2
- Application number: 17/355,433
- Filed: 2021-06-23
- Published: 2021-10-14
- Granted: 2024-06-18
- Earliest claimed: 2018-02-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shang-Yun Hou; Sung-Hui Huang; Kuan-Yu Huang; Hsien-Pin Hu; Yushun Lin; Heh-Chang Huang; Hsing-Kuo Hsia; Chih-Chieh Hung; Ying-Ching Shih; Chin-Fu Kao; Wen-Hsin Wei; Li-Chung Kuo; Chi-Hsi Wu; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US12015023B2

## CPC

- H10W 90/00: Package configurations
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/071: {Connecting or disconnecting}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 76/47: Solid or gel fillings
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01236: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07327: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/07353: {changes in shapes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/30: Die-attach connectors
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/853: {On the same surface}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/90: Bond pads, in general
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

## Claims

### Claim 1

A package comprising:
a substrate;
a first integrated circuit die bonded to a first side of the substrate;
an annular structure bonded to the first side of the substrate adjacent the first integrated circuit die, wherein the first integrated circuit die is outside an outermost perimeter of the annular structure;
an encapsulant over the substrate and surrounding the annular structure and the first integrated circuit die, a topmost surface of the encapsulant being level with a topmost surface of the annular structure and a topmost surface of the first integrated circuit die; and
a functional component within the annular structure and bonded to the first side of the substrate, wherein the annular structure is between the encapsulant and the functional component.

### Claim 2 (depends on 1)

The package of claim 1, further comprising an adhesive interposed between the first side of the substrate and the annular structure.

### Claim 3 (depends on 1)

The package of claim 1, further comprising a plurality of connectors on a second side of the substrate, the second side of the substrate being opposite the first side of the substrate.

### Claim 4 (depends on 1)

The package of claim 1, wherein the substrate comprises an interposer.

### Claim 5 (depends on 1)

The package of claim 1, wherein the functional component comprises a second integrated circuit die.

### Claim 6 (depends on 1)

The package of claim 1, wherein the functional component and the annular structure have different heights.

### Claim 7 (depends on 1)

The package of claim 1, wherein the annular structure is functionally inert.

### Claim 8

A package comprising:
a substrate;
a first integrated circuit die bonded to a first side of the substrate;
a second integrated circuit die bonded to the first side of the substrate adjacent the first integrated circuit die;
an annular structure bonded to the first side of the substrate adjacent the second integrated circuit die;
a first encapsulant over the substrate and surrounding the annular structure, the first integrated circuit die and the second integrated circuit die, wherein a topmost surface of the first encapsulant is level with a topmost surface of the annular structure, a topmost surface of the first integrated circuit die and a topmost surface of the second integrated circuit die;
a functional component within the annular structure and bonded to the first side of the substrate; and
a second encapsulant within the annular structure and extending along sidewalls of the functional component.

### Claim 9 (depends on 8)

The package of claim 8, wherein a topmost surface of the second encapsulant is below the topmost surface of the annular structure.

### Claim 10 (depends on 8)

The package of claim 8, wherein the functional component comprises a third integrated circuit die.

### Claim 11 (depends on 8)

The package of claim 8, wherein a topmost surface of the functional component is above the topmost surface of the annular structure.

### Claim 12 (depends on 8)

The package of claim 8, wherein the annular structure is free of active and passive devices.

### Claim 13 (depends on 8)

The package of claim 8, wherein the first integrated circuit die and the second integrated circuit die have different widths.

### Claim 14

A package comprising:
a substrate;
a first integrated circuit die bonded to a first side of the substrate;
a second integrated circuit die bonded to the first side of the substrate adjacent the first integrated circuit die;
an annular structure bonded to a topmost surface of the substrate;
a first encapsulant over the substrate and surrounding the annular structure, the first integrated circuit die and the second integrated circuit die, wherein a topmost surface of the first encapsulant is level with a topmost surface of the annular structure and a topmost surface of the second integrated circuit die;
a functional component within the annular structure and bonded to the first side of the substrate, wherein the annular structure is between the first encapsulant and the functional component; and
a second encapsulant within the annular structure and extending along sidewalls of the functional component.

### Claim 15 (depends on 14)

The package of claim 14, wherein a topmost surface of the functional component is above the topmost surface of the first encapsulant.

### Claim 16 (depends on 14)

The package of claim 14, further comprising a plurality of connectors electrically and mechanically coupling the functional component to the first integrated circuit die.

### Claim 17 (depends on 14)

The package of claim 14, further comprising an underfill over the substrate and extending along sidewalls of the first integrated circuit die and sidewalls of the second integrated circuit die, wherein a topmost surface of the underfill is below the topmost surface of the first encapsulant.

### Claim 18 (depends on 14)

The package of claim 14, further comprising an adhesive interposed between the first side of the substrate and the annular structure.

### Claim 19 (depends on 14)

The package of claim 14, wherein the substrate comprises a plurality of through vias.

### Claim 20 (depends on 14)

The package of claim 14, wherein an upper surface of the second encapsulant is lower than an upper surface of the first encapsulant.