# US 12,015,019 B2 · Stacked die multichip module package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,019 B2 - Document ID: US12015019B2 - Status: Granted - Kind: B2 - Application number: 17/357,459 - Filed: 2021-06-24 - Published: 2021-10-14 - Granted: 2024-06-18 - Earliest claimed: 2019-09-18 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Jonathan Almeria Noquil; Makarand Ramkrishna Kulkarni - Web page: https://patentgrep.com/patent/US12015019B2 ## CPC - H10W 90/00: Package configurations - H10W 90/811: {Multiple chips on leadframes} - H10W 40/778: {in encapsulations} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00} - H10W 70/685: comprising multiple insulating layers - H10W 72/0198: {batch processes} - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 70/695: Organic materials - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer. ## Claims ### Claim 1 A semiconductor apparatus, comprising: a multilayer routable lead frame substrate (MRLF substrate) including a first routable lead frame (RLF) layer and at least a second RLF layer, the MRLF substrate having a top side and a bottom side with a multilayer extending via extending from a top side of the first RLF layer at least into the second RLF layer; a first vertical device, wherein a side of the first vertical device is flipchip attached to a bottom side of the second RLF layer; a second vertical device, wherein a side of the second vertical device is flipchip attached to the bottom side of the second RLF layer lateral to the first vertical device and is contacting the multilayer extending via; a top mold compound on the top side of the MRLF substrate lateral to a metal pad on the multilayer extending via, and a bottom mold compound layer on the bottom side of the second RLF layer, wherein a bottom side of the first vertical device and a bottom side of the second vertical device are both exposed by the bottom mold compound layer. ### Claim 2 (depends on 1) The semiconductor apparatus of claim 1, wherein the first vertical device comprises a first vertical power field effect transistor (FET) and wherein the second vertical device comprises a second vertical power FET, further comprising a dielectric layer within the second RLF layer for isolation between a source of the second vertical power FET and a drain of the first vertical power FET. ### Claim 3 (depends on 2) The semiconductor apparatus of claim 2, further comprising a metal contact layer coupling a drain of the second vertical power FET to a source of the first vertical power FET to provide a switching node for the semiconductor apparatus. ### Claim 4 (depends on 1) The semiconductor apparatus of claim 1, wherein the metal pad comprises copper. ### Claim 5 (depends on 2) The semiconductor apparatus of claim 2, wherein the second RLF layer includes a connection for providing a node that capacitively couples together a drain of the first vertical power FET and a source of the second vertical power FET. ### Claim 6 (depends on 1) The semiconductor apparatus of claim 1, wherein a dielectric for the first RLF layer and the second RLF layer each provide a 25° C. thermal conductivity of at least 1 W/m·K. ### Claim 7 (depends on 1) The semiconductor apparatus of claim 1, wherein the first vertical power FET and the second vertical power FET both comprise silicon-based n-channel devices. ### Claim 8 (depends on 1) The semiconductor apparatus of claim 1, wherein the semiconductor apparatus comprises a leadless package. ### Claim 9 A semiconductor apparatus, comprising: a multilayer routable lead frame substrate (MRLF substrate) including a first routable lead frame (RLF) layer and at least a second RLF layer, the MRLF substrate having a top side and a bottom side with a multilayer extending via extending from a top side of the first RLF layer at least into the second RLF layer; a first vertical power field effect transistor (FET) including a first drain and a first source, wherein a side of the first vertical power FET is flipchip attached to a bottom side of the second RLF layer; a second vertical power (FET) including a second drain and a second source, wherein a side of the second vertical power FET having the second source is flipchip is attached to the bottom side of the second RLF layer lateral to the first vertical power FET and is contacting the multilayer extending via; a top mold compound on the top side of the MRLF substrate lateral to a metal pad on the multilayer extending via, and a bottom mold compound layer on the bottom side of the second RLF layer, wherein a bottom side of the first vertical power FET and the second vertical power FET are both exposed by the bottom mold compound layer. ### Claim 10 (depends on 9) The semiconductor apparatus of claim 9, further comprising a dielectric layer within the second RLF layer for isolation between the second source and the first drain. ### Claim 11 (depends on 9) The semiconductor apparatus of claim 9, further comprising a metal contact layer coupling the second drain to the first source to provide a switching node for the Semiconductor apparatus. ### Claim 12 (depends on 9) The semiconductor apparatus of claim 9, wherein the second RLF layer includes a connection for providing a node that capacitively couples together the first drain and the second source. ### Claim 13 A method, comprising: forming a first routable lead frame (RLF) layer and at least a second RLF layer having a top side and a bottom side including a multilayer extending via that extends from the top side at least into the second RLF layer; forming a metal pad over the multilayer extending via; molding to form a top mold compound layer on the second RLF layer to expose the metal pad; flipchip attaching a first vertical device and a second vertical device to the bottom side of the second RLF layer; and molding to form a bottom mold compound layer on the bottom side of the second RLF layer after the flipchip attaching, wherein bottom sides of the first and second vertical devices are exposed by the bottom mold compound layer. ### Claim 14 (depends on 13) The method of claim 13, wherein the first vertical device comprises a first vertical power field effect transistor (FET) and wherein the second vertical device comprises a second vertical power FET, further comprising a dielectric layer within the second RLF layer for isolation between a source of the second vertical power FET and a drain of the first vertical power FET. ### Claim 15 (depends on 14) The method of claim 14, further comprising forming a metal contact layer coupling a drain of the second vertical power FET to a source of the first vertical power FET to provide a switching node. ### Claim 16 The method of 13, wherein the metal pad comprises copper. ### Claim 17 (depends on 13) The method of claim 13, further comprising forming the second RLF layer including positioning a dielectric layer between a drain of the first vertical power FET and a source of the second vertical power FET. ### Claim 18 (depends on 13) The method of claim 13, wherein at least one of the molding to form the top mold compound layer and wherein the molding to form the bottom mold compound layer comprises a film assisted molding process. ### Claim 19 (depends on 13) The method of claim 13, wherein a dielectric material for the first RLF layer and the second RLF layer each provide a 25° C. thermal conductivity of at least 1 W/m·K. ### Claim 20 (depends on 14) The method of claim 14, wherein the first vertical power FET and the second vertical power FETs both comprise silicon-based n-channel devices.