# US 12,015,017 B2 · Package structure, package-on-package structure and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,017 B2 - Document ID: US12015017B2 - Status: Granted - Kind: B2 - Application number: 17/321,528 - Filed: 2021-05-17 - Published: 2021-09-02 - Granted: 2024-06-18 - Earliest claimed: 2018-08-14 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chih-Hsuan Tai; Hao-Yi Tsai; Yu-Chih Huang; Chia-Hung Liu; Ting-Ting Kuo; Ban-Li Wu; Ying-Cheng Tseng; Chi-Hui Lai - Web page: https://patentgrep.com/patent/US12015017B2 ## CPC - H10P 72/74: {using temporarily an auxiliary support} - H10W 90/00: Package configurations - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/50: Bond wires - H10W 72/874: {On different surfaces} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/9413: {on encapsulations} - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant. ## Claims ### Claim 1 A structure, comprising: a backside redistribution layer, comprising: a dielectric layer having a first surface and a second surface; a first group of connecting portions embedded in the dielectric layer, wherein the first group of connecting portions has beveled sidewalls and has a width that increases from the first surface to the second surface; a second group of connecting portions embedded in the dielectric layer, wherein the second group of connecting portions has beveled sidewalls and has a width that decreases from the first surface to the second surface; a top redistribution layer electrically connected to the backside redistribution layer; and a semiconductor die sandwiched in between the backside redistribution layer and the top redistribution layer, and electrically connected to the top redistribution layer. ### Claim 2 (depends on 1) The structure according to claim 1, wherein the backside redistribution layer further comprises a conductive layer disposed on the first surface of the dielectric layer and connected to the first group of connecting portions and connected to the second group of connecting portions. ### Claim 3 (depends on 2) The structure according to claim 2, wherein an angle of the beveled sidewalls of the first group of connecting portions relative to the conductive layer is greater than 90°, and an angle of the beveled sidewalls of the second group of connecting portions relative to the conductive layer is smaller than 90°. ### Claim 4 (depends on 2) The structure according to claim 2, further comprising a third group of connecting portions embedded in the dielectric layer, wherein an angle of sidewalls of the third group of connecting portions relative to the conductive layer is approximately 90°. ### Claim 5 (depends on 2) The structure according to claim 2, further comprising a plurality of conductive terminals connected to the first group of connecting portions and connected to the second group of connecting portions opposite to a side where the conductive layer is connected to. ### Claim 6 (depends on 2) The structure according to claim 2, further comprising a plurality of through vias joining the conductive layer to the top redistribution layer. ### Claim 7 (depends on 1) The structure according to claim 1, wherein the first group of connecting portions and the second group of connecting portions have different sizes and different joint pattern shapes. ### Claim 8 A structure, comprising: a first redistribution layer, wherein the first redistribution layer comprises: a conductive layer embedded in a first dielectric layer; a plurality of connecting portions embedded in a second dielectric layer, wherein the second dielectric layer is directly disposed on the first dielectric layer, and the plurality of connecting portions is directly joined with a surface of the conductive layer, the plurality of connecting portions comprises joint patterns with two or more different shapes, including at least one circular joint pattern and at least one trapezoidal joint pattern that are exposed at a surface of the second dielectric layer, and a height of the plurality of connecting portions is greater than a thickness of the conductive layer; a semiconductor die disposed on the first dielectric layer; through insulator vias disposed on the first dielectric layer and electrically connected to the conductive layer; and a plurality of metallization layers electrically connected to the semiconductor die and the through insulator vias. ### Claim 9 (depends on 8) The structure according to claim 8, wherein a surface of the joint patterns of the plurality of connecting portions is coplanar with the surface of the second dielectric layer. ### Claim 10 (depends on 8) The structure according to claim 8, wherein the joint patterns with two or more different shapes further includes at least one square shaped joint pattern, at least one semicircular joint pattern and at least one diamond-shaped joint pattern. ### Claim 11 (depends on 8) The structure according to claim 8, wherein the thickness of the conductive layer and the height of the plurality of connecting portions sums up to a range of 14 μm to 35 μm. ### Claim 12 (depends on 8) The structure according to claim 8, further comprising a plurality of conductive terminals disposed on the joint patterns of the plurality of connecting portions. ### Claim 13 (depends on 12) The structure according to claim 12, wherein the conductive terminals are selected from the group consisting of a solder ball, an organic solder preservative, a nickel-gold coating, a titanium coating and a silver paste. ### Claim 14 (depends on 8) The structure according to claim 8, wherein the plurality of connecting portions includes: a first group of connecting portions having beveled sidewalls, and an angle of the beveled sidewalls of the first group of connecting portions relative to the conductive layer is greater than 90°; and a second group of connecting portions having beveled sidewalls, and an angle of the beveled sidewalls of the second group of connecting portions relative to the conductive layer is smaller than 90°. ### Claim 15 A package-on-package structure, comprising: a first package, the first package comprises: a plurality of connecting portions embedded in a first dielectric layer, wherein the plurality of connecting portions has a first side, a second side, and sidewalls joining the first side to the second side, the first side of the plurality of connecting portions is exposed from and coplanar with a first surface of the first dielectric layer; a conductive layer joined with the second side of the plurality of connecting portions; and a semiconductor die disposed over the first dielectric layer; a second package stacked on the first package, wherein the second package is electrically connected to the first side of the plurality of connecting portions through a plurality of conductive balls; an underfill disposed on the first dielectric layer and surrounding the plurality of conductive balls, wherein an interface between the underfill and the first dielectric layer is aligned with an interface between the plurality of conductive balls and the first side of the plurality of connecting portions; and a silver paste disposed on the first side of one of the connecting portions in between the first package and the second package, wherein the plurality of conductive balls of the second package surrounds the silver paste, and the underfill further surrounds and contact sidewalls of the silver paste. ### Claim 16 (depends on 15) The package-on-package structure according to claim 15, wherein the interface between the underfill and the first dielectric layer is further aligned with an interface between the silver paste and the first side of the plurality of connecting portions. ### Claim 17 (depends on 15) The package-on-package structure according to claim 15, wherein the first side of the plurality of connecting portions include at least one or more joint patterns selected from the group consisting of a circular joint pattern, a diamond-shaped joint pattern, a semicircular joint pattern, a trapezoidal-shaped joint pattern and a squared-shaped joint pattern. ### Claim 18 (depends on 15) The package-on-package structure according to claim 15, wherein the plurality of connecting portions includes: a first group of connecting portions having beveled sidewalls joining the first side to the second side, and an angle of the beveled sidewalls of the first group of connecting portions relative to the conductive layer is greater than 90°; and a second group of connecting portions having beveled sidewalls joining the first side to the second side, and an angle of the beveled sidewalls of the second group of connecting portions relative to the conductive layer is smaller than 90°. ### Claim 19 (depends on 15) The package-on-package structure according to claim 15, wherein the first package further comprises: an insulating encapsulant surrounding the semiconductor die; and through insulator vias embedded in the insulating encapsulant, and electrically connecting the semiconductor die to the conductive layer. ### Claim 20 (depends on 15) The package-on-package structure according to claim 15, wherein the second package comprises a plurality of semiconductor chips, and wherein the silver paste is disposed on the second package and non-overlapped with the plurality of semiconductor chips.