# US 12,015,015 B2 · Semiconductor package and semiconductor module including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,015 B2 - Document ID: US12015015B2 - Status: Granted - Kind: B2 - Application number: 18/108,503 - Filed: 2023-02-10 - Published: 2023-06-22 - Granted: 2024-06-18 - Earliest claimed: 2021-04-19 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Byung Jun Bang; Ju Il Eom - Web page: https://patentgrep.com/patent/US12015015B2 ## CPC - H10W 90/00: Package configurations - H05K 1/181: associated with surface mounted components - H10W 70/63: Vias, e.g. via plugs - H10W 70/656: Fan-in layouts - H10W 72/01515: {Forming coatings} - H10W 72/075: {of bond wires} - H10W 72/07552: {changes in structures or sizes} - H10W 72/07554: {changes in dispositions} - H10W 72/521: {Structures or relative sizes of bond wires} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/547: {Dispositions of multiple bond wires} - H10W 72/5473: {multiple bond wires connected to a common bond pad} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/732: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A semiconductor package includes a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire. ## Claims ### Claim 1 A semiconductor package comprising: a substrate including a first bonding pad and a first conductive pattern, wherein the first bonding pad is in contact with the first conductive pattern; a lower semiconductor chip stacked over the substrate, wherein the lower semiconductor chip includes a first lower chip pad; an upper semiconductor chip stacked over the lower semiconductor chip, wherein the upper semiconductor chip includes a first upper chip pad; a first lower bonding wire connecting the first bonding pad to the first lower chip pad; and a first upper bonding wire connecting the first bonding pad to the first upper chip pad, wherein the first bonding pad is positioned between the first conductive pattern and the first semiconductor chip, wherein the first lower bonding wire is connected to a first portion of the first bonding pad and the first upper bonding wire is connected to a second portion of the first bonding pad, and wherein the first portion of the first bonding pad is farther from the first conductive pattern than the second portion of the first bonding pad. ### Claim 2 (depends on 1) The semiconductor package according to claim 1, wherein a length of the first upper bonding wire is longer than a length of the first lower bonding wire. ### Claim 3 (depends on 2) The semiconductor package according to claim 2, wherein a distance between the first portion and the second portion compensates for a length difference between the first upper bonding wire and the first lower bonding wire. ### Claim 4 (depends on 1) The semiconductor package according to claim 1, further comprising a second lower bonding wire and a second upper bonding wire, wherein the substrate further includes a second bonding pad and a second conductive pattern, wherein the second bonding pad is in contact with the second conductive pattern, wherein the lower semiconductor chip further includes a second lower chip pad, wherein the upper semiconductor chip further includes a second upper chip pad, wherein the second lower bonding wire connects the second bonding pad to the second lower chip pad, wherein the second upper bonding wire connects the second bonding pad to the second upper chip pad, wherein the second bonding pad is positioned between the second conductive pattern and the second semiconductor chip, wherein the second lower bonding wire is connected to a first portion of the second bonding pad and the second upper bonding wire is connected to a second portion of the second bonding pad, and wherein the first portion of the second bonding pad is farther from the second conductive pattern than the second portion of the second bonding pad. ### Claim 5 (depends on 4) The semiconductor package according to claim 4, wherein a length of the second upper bonding wire is longer than a length of the second lower bonding wire. ### Claim 6 (depends on 4) The semiconductor package according to claim 4, wherein a distance between the third portion and the fourth portion compensates for a length difference between the second upper bonding wire and the second lower bonding wire. ### Claim 7 (depends on 4) The semiconductor package according to claim 4, wherein the first bonding pad and the first conductive pattern are positioned in a first region of the substrate, close to a first lower edge of the lower semiconductor chip, wherein the second bonding pad and the second conductive pattern are positioned in a second region of the substrate, close to a second lower edge of the lower semiconductor chip, and wherein the first lower edge of the lower semiconductor chip and the second lower edge of the lower semiconductor chip are opposite to each other. ### Claim 8 (depends on 4) The semiconductor package according to claim 4, wherein the first semiconductor chip and the second semiconductor chip are positioned between the first bonding pad and the second bonding pad. ### Claim 9 A semiconductor package comprising: a substrate including a first bonding pad exposed on a top surface of the substrate and a first conductive via formed within the substrate, wherein the first bonding pad and the first conductive via are electrically connected to each other; a first semiconductor chip stacked over the substrate; a second semiconductor chip stacked over the first semiconductor chip, wherein the first semiconductor chip includes a first chip pad exposed on a top surface of the first semiconductor chip, and wherein the second semiconductor chip includes a second chip pad exposed on a top surface of the second semiconductor chip; a first bonding wire connecting the first bonding pad to the first chip pad; and a second bonding wire connecting the first bonding pad to the second chip pad, wherein the first bonding wire is bonded to a first portion of the first bonding pad, wherein the second bonding wire is bonded to a second portion of the first bonding pad, and wherein a first distance between the first conductive via and the first portion of the first bonding pad is longer than a second distance between the first conductive via and the second portion of the first bonding pad. ### Claim 10 (depends on 9) The semiconductor package according to claim 9, wherein the substrate further includes a first conductive pattern between the first bonding pad and the first conductive via, and wherein the first conductive pattern electrically connects the first bonding pad to the first conductive via. ### Claim 11 (depends on 10) The semiconductor package according to claim 10, wherein a sidewall of the first bonding pad is in contact with a sidewall of the first conductive pattern. ### Claim 12 (depends on 10) The semiconductor package according to claim 10, wherein the first conductive pattern is in contact with the first conductive via. ### Claim 13 A semiconductor module comprising: a module substrate; a semiconductor package stacked over the module substrate; a package substrate including a first bonding pad exposed on a top surface of the package substrate and a first conductive via formed within the package substrate; a semiconductor chip stack stacked over the package substrate, wherein the semiconductor chip stack includes a first chip pad and a second chip pad, a first bonding wire electrically connecting the first bonding pad to the first chip pad; and a second bonding wire electrically connecting the first bonding pad to the second chip pad, wherein the first bonding wire is bonded to a first portion of the first bonding pad, wherein the second bonding wire is bonded to a second portion of the first bonding pad, wherein a first length of the first bonding wire is shorter than a second length of the second bonding wire, and wherein a first distance between the first conductive via and the first portion of the first bonding pad is longer than a second distance between the first conductive via and the second portion of the first bonding pad. ### Claim 14 (depends on 13) The semiconductor module according to claim 13, wherein the semiconductor chip stack includes a first semiconductor chip and a second semiconductor chip stacked over the first semiconductor chip, wherein the first chip pad is disposed on a top surface of the first semiconductor chip, and the second chip pad is disposed on a top surface of the second semiconductor chip. ### Claim 15 (depends on 13) The semiconductor module according to claim 13, wherein the second portion of the first bonding pad is closer to the first conductive via than the first portion of the first bonding pad, and wherein the first portion of the first bonding pad is closer to the semiconductor chip stack than the second portion of the first bonding pad. ### Claim 16 (depends on 13) The semiconductor package according to claim 13, wherein the package substrate further includes a first conductive pattern between the first bonding pad and the first conductive via, and wherein the first conductive pattern electrically connects the first bonding pad to the first conductive via. ### Claim 17 (depends on 16) The semiconductor package according to claim 16, wherein a sidewall of the first bonding pad is in contact with a sidewall of the first conductive pattern. ### Claim 18 (depends on 16) The semiconductor package according to claim 16, wherein the first conductive pattern is in contact with the first conductive via.