# US 12,015,014 B2 · Semiconductor package

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- Number: US 12,015,014 B2
- Document ID: US12015014B2
- Status: Granted
- Kind: B2
- Application number: 17/679,861
- Filed: 2022-02-24
- Published: 2022-06-09
- Granted: 2024-06-18
- Earliest claimed: 2019-12-13
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Doohwan Lee; Jungsoo Byun
- Web page: https://patentgrep.com/patent/US12015014B2

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 90/00: Package configurations
- H10W 40/10: Arrangements for heating
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 76/161: {Containers comprising no base}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/853: {On the same surface}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/9413: {on encapsulations}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.

## Claims

### Claim 1

A semiconductor package, comprising:
a plurality of semiconductor chips comprising a first semiconductor chip having a first active surface on which first connection pads are disposed and a first inactive surface opposing the first active surface, and a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which second connection pads are disposed and a second inactive surface opposing the second active surface,
a first adhesive layer disposed below the second inactive surface of the second semiconductor chip;
first bumps disposed directly on the first connection pads;
second bumps disposed directly on the second connection pads;
at least one first dummy bump directly on the first active surface of the first semiconductor chip and spaced apart from the first bumps;
a first filling layer covering the first active surface of the first semiconductor chip, side surfaces of the first bumps, and side surfaces of the at least one first dummy bump; and
at least one second dummy bump directly on the second active surface of the second semiconductor chip and spaced apart from the second bumps,
wherein the first bump does not overlap the second semiconductor chip in a vertical direction perpendicular to an upper surface of the first semiconductor chip, and
wherein the first adhesive layer is in contact with the second semiconductor chip, the first filling layer, and the at least one first dummy bump.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein an upper surface of the at least one first dummy bump is substantially coplanar with upper surfaces of the first bumps.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the at least one first dummy bump overlaps the second semiconductor chip in a vertical direction perpendicular to an upper surface of the first semiconductor chip.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein a width of the at least one first dummy bump is greater than a width of one of the first bumps.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the at least one first dummy bump includes a plurality of first dummy bumps spaced apart from each other.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the first adhesive layer is spaced apart from the first bump.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, further comprising:
a second filling layer covering the second active surface of the semiconductor chip, side surfaces of the second bumps, and side surfaces of the at least one second dummy bump.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, further comprising:
a first insulating layer covering side surfaces of the first bump and the at least on first dummy bump on the first active surface of the first semiconductor chip; and
a first filling layer covering side surfaces of the first insulating layer and side surfaces of the first semiconductor chip.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, further comprising:
a connection member disposed between the first semiconductor chip and the second semiconductor chip, the connection member comprising redistribution layers electrically connected to the first bumps.

### Claim 10

A semiconductor package, comprising:
a plurality of semiconductor chips comprising a first semiconductor chip having a first active surface on which first connection pads are disposed and a first inactive surface opposing the first active surface, and a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which second connection pads are disposed and a second inactive surface opposing the second active surface;
a support member having a side surface facing a side surface of the first semiconductor chip;
first bumps disposed directly on the first connection pads;
first posts disposed directly on the first bumps and electrically connected to the first connection pads;
first dummy posts disposed side by side with the first posts and overlapping the support member in a vertical direction perpendicular to an upper surface of the first semiconductor chip; and
a connection member on the plurality of semiconductor chips and comprising redistribution layers electrically connected to each of the first and second posts.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein upper surfaces of the first posts are substantially coplanar with upper surfaces of the first dummy posts.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, further comprising:
a first filling layer covering the first active surface of the first semiconductor chip and side surfaces of the first bumps; and
a second filling layer covering the second active surface of the semiconductor chip, side surfaces of the first posts, and side surfaces of the first dummy posts.

### Claim 13 (depends on 10)

The semiconductor package of claim 10, further comprising:
second posts disposed on the first posts, one of the second posts having a width different from a width of one of the first posts.

### Claim 14 (depends on 10)

The semiconductor package of claim 10, further comprising:
second bumps disposed directly on the second connection pads;
second posts disposed directly on the second bumps and electrically connected to the second connection pads; and
second dummy posts disposed side by side with the second posts and not overlapping the semiconductor chip in the vertical direction.

### Claim 15 (depends on 10)

The semiconductor package of claim 10, wherein the support member includes a plurality of insulating layers, a plurality of wiring layers buried in the insulating layers, and a plurality of vias electrically connecting the plurality of wiring layers to one another.

### Claim 16

A semiconductor package, comprising:
a plurality of semiconductor chips;
a plurality of filling layers surrounding side surfaces of the plurality of semiconductor chips, respectively;
a connection member disposed on the plurality of filling layers;
a plurality of posts disposed in the plurality of filling layers; and
a plurality of bumps electrically connected to the plurality of semiconductor chips, respectively,
wherein the plurality of semiconductor chips comprises a first semiconductor chip and a second semiconductor chip partially overlapping the first semiconductor chip,
wherein the plurality of filling layers comprises a first filling layer surrounding a side surface of the first semiconductor chip and a second filling layer surrounding a side surface of the second semiconductor chip,
wherein the plurality of bumps comprises a first bump electrically connected to a first connection pad of the first semiconductor chip, and a second bump electrically connected to a second connection pad of the second semiconductor chip, and
wherein the plurality of posts comprises a first post penetrating the second filling layer on the first filling layer and electrically connected to the first bump, and a plurality of dummy posts penetrating the second filling layer.

### Claim 17 (depends on 16)

The semiconductor package of claim 16,
wherein the plurality of semiconductor chips further comprises a third semiconductor chip disposed on the second semiconductor chip, and a fourth semiconductor chip disposed on the third semiconductor chip,
wherein the plurality of filling layers further comprises a third filling layer surrounding a side surface of the third semiconductor chip, and a fourth filling layer surrounding a side surface of the fourth semiconductor chip,
wherein the plurality of bumps further comprises a third bump electrically connected to a third connection pad of the third semiconductor chip, and a fourth bump electrically connected to a fourth connection pad of the fourth semiconductor chip, and
wherein the plurality of posts further comprises a second post penetrating the third filling layer on the second filling layer and electrically connected to the second bump, and a third post penetrating the fourth filling layer on the third filling layer and electrically connected to the third bump.