# US 12,015,013 B2 · Die stack structure, semiconductor structure and method of fabricating the same

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- Number: US 12,015,013 B2
- Document ID: US12015013B2
- Status: Granted
- Kind: B2
- Application number: 17/676,239
- Filed: 2022-02-21
- Published: 2022-06-09
- Granted: 2024-06-18
- Earliest claimed: 2020-05-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ming-Fa Chen; Chao-Wen Shih; Min-Chien Hsiao; Nien-Fang Wu; Sung-Feng Yeh; Tzuan-Horng Liu
- Web page: https://patentgrep.com/patent/US12015013B2

## CPC

- H10W 90/00: Package configurations
- H10D 62/117: {Shapes of semiconductor bodies}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 72/0198: {batch processes}
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/019: {of bond pads}
- H10W 72/075: {of bond wires}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/551: {Materials of bond wires}
- H10W 72/874: {On different surfaces}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 80/016: {Cleaning}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.

## Claims

### Claim 1

A die stack structure, comprising:
a bottom tier semiconductor die comprising a semiconductor substrate and an interconnect structure, the semiconductor substrate comprising a first portion and a second portion disposed on the first portion, the interconnect structure being disposed on a top surface of the second portion, a lateral dimension of the first portion being greater than a lateral dimension of the top surface of the second portion;
a top tier semiconductor die bonded to the bottom tier semiconductor die;
an insulating encapsulation disposed on the first portion and laterally encapsulating the second portion and the top tier semiconductor die; and
a redistribution circuit structure electrically connected with the bottom tier semiconductor die and the top tier semiconductor die, wherein the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.

### Claim 2 (depends on 1)

The die stack structure as claimed in claim 1, wherein the insulating encapsulation covers sidewalls of the second portion, and sidewalls of the insulating encapsulation are substantially aligned with sidewalls of the first portion.

### Claim 3 (depends on 1)

The die stack structure as claimed in claim 1, wherein the bottom tier semiconductor die comprises through semiconductor vias electrically connected with the redistribution circuit structure.

### Claim 4 (depends on 3)

The die stack structure as claimed in claim 3, wherein the bottom tier semiconductor substrate further comprises a third portion, the first portion is located between the second portion and the third portion, the first portion contacts a top surface of the third portion, the lateral dimension of the first portion is greater than a lateral dimension of a bottom surface of the third portion, and the top surface of the third portion is opposite to the bottom surface of the third portion.

### Claim 5 (depends on 1)

The die stack structure as claimed in claim 1, wherein the insulating encapsulation comprises a body portion and a ring portion, the body portion laterally encapsulates the top tier semiconductor die, and the ring portion extends along sidewalls of the interconnect structure and the sidewalls of the second portion.

### Claim 6 (depends on 5)

The die stack structure as claimed in claim 5, wherein the top tier semiconductor die comprises through semiconductor vias electrically connected to the redistribution circuit structure.

### Claim 7 (depends on 6)

The die stack structure as claimed in claim 6, wherein the body portion of the insulating encapsulation comprises a top portion and a bottom portion, the redistribution circuit structure is in contact with a top surface of the top portion, and a lateral dimension of the bottom portion is greater than a lateral dimension of the top surface of the top portion.

### Claim 8

A package structure, comprising:
a first semiconductor die comprising a first semiconductor substrate and a first interconnect structure, the first semiconductor substrate comprising a first portion and a second portion disposed on the first portion, the first interconnect structure being disposed on a top surface of the second portion, a lateral dimension of the first portion being greater than a lateral dimension of the top surface of the second portion;
a second semiconductor die comprising a second semiconductor substrate and a second interconnect structure disposed on the second semiconductor substrate, the second semiconductor die being electrically connected with and bonded to the first semiconductor die;
a first insulating encapsulation disposed on the first portion of the first semiconductor substrate, and laterally encapsulating the second semiconductor die and the second portion of the first semiconductor substrate;
a first redistribution circuit structure electrically connected with the first semiconductor die and the second semiconductor die, wherein the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure;
a second insulating encapsulation laterally encapsulating the first insulating encapsulation, the first portion and the first redistribution circuit structure; and
a second redistribution circuit structure disposed on the first redistribution circuit structure and the second insulating encapsulation, and electrically connected with the first redistribution circuit structure.

### Claim 9 (depends on 8)

The package structure as claimed in claim 8, wherein the first insulating encapsulation covers sidewalls of the second portion of the first semiconductor substrate, sidewalls of the first insulating encapsulation are substantially aligned with sidewalls of the first portion of the first semiconductor substrate, and the second insulating encapsulation covers sidewalls of the first portion of the first semiconductor substrate and sidewalls of first redistribution circuit structure.

### Claim 10 (depends on 8)

The package structure as claimed in claim 8, wherein the first insulating encapsulation comprises a body portion and a ring portion, the body portion laterally encapsulates the second semiconductor die, the ring portion extends along sidewalls of the first interconnect structure, and the sidewalls of the second portion of the first semiconductor substrate.

### Claim 11 (depends on 8)

The package structure as claimed in claim 8, further comprising through insulator vias penetrating the second insulating encapsulation, and electrically connected with the second redistribution circuit structure.

### Claim 12 (depends on 8)

The package structure as claimed in claim 8, wherein the first semiconductor die comprises through semiconductor vias electrically connected to the first redistribution circuit structure.

### Claim 13 (depends on 12)

The package structure as claimed in claim 12, wherein the first semiconductor substrate further comprises a third portion, the first portion is located between the second portion and the third portion, the first portion contacts a top surface of the third portion, the lateral dimension of the first portion is greater than a lateral dimension of a bottom surface of the third portion, the top surface of the third portion is opposite to the bottom surface of the third portion, and the second insulating encapsulation covers sidewalls of the third portion of the first semiconductor substrate.

### Claim 14 (depends on 8)

The package structure as claimed in claim 8, wherein the second semiconductor die comprises through semiconductor vias electrically connected to the first redistribution circuit structure.

### Claim 15 (depends on 14)

The package structure as claimed in claim 14, wherein the body portion of the first insulating encapsulation comprises a top portion and a bottom portion, the first redistribution circuit structure is in contact with a top surface of the top portion, a lateral dimension of the bottom portion is greater than a lateral dimension of the top surface of the top portion, and the second insulating encapsulation covers sidewalls of the top portion of the body portion of the first insulating encapsulation.

### Claim 16

A die stack structure, comprising:
a first semiconductor die comprising a first portion and a second portion, wherein the first portion is wider than the second portion;
a second semiconductor die disposed on the second portion and electrically connected to the first semiconductor die;
an insulating encapsulation laterally encapsulating the second semiconductor die and the second portion of the first semiconductor die; and
a redistribution circuit structure electrically connected to the first semiconductor die and the second semiconductor die, wherein the first portion is wider than the redistribution circuit structure.

### Claim 17 (depends on 16)

The die stack structure of claim 16, wherein the insulating encapsulation covers sidewalls of the second portion, and sidewalls of the insulating encapsulation are substantially aligned with sidewalls of the first portion.

### Claim 18 (depends on 16)

The die stack structure of claim 16, wherein the first semiconductor die comprises through semiconductor vias electrically connected with the redistribution circuit structure.

### Claim 19 (depends on 16)

The die stack structure of claim 16, wherein the first semiconductor substrate further comprises a third portion, the first portion is located between the second portion and the third portion, the first portion is wider than the third portion, and the third portion is located between the first portion and the redistribution circuit structure.

### Claim 20 (depends on 16)

The die stack structure of claim 16, wherein the insulating encapsulation comprises a body portion and a ring portion, the body portion laterally encapsulates the second semiconductor die, and the ring portion extends along sidewalls of the second portion.