# US 12,015,012 B2 · Semiconductor device

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- Number: US 12,015,012 B2
- Document ID: US12015012B2
- Status: Granted
- Kind: B2
- Application number: 17/613,605
- Filed: 2020-05-25
- Published: 2022-07-28
- Granted: 2024-06-18
- Earliest claimed: 2019-06-07
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Tatsuya Onuki; Takanori Matsuzaki; Yuki Okamoto; Shunpei Yamazaki
- Web page: https://patentgrep.com/patent/US12015012B2

## CPC

- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10W 90/00: Package configurations
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4094: Bit-line management or control circuits
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/40: of conductive or resistive materials
- H10W 20/01: {Manufacture or treatment}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10W 72/07236: {Soldering or alloying}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/20: Configurations of stacked chips
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon substrate including a first circuit;
a first element layer over the silicon substrate; and
a second element layer over the first element layer,
wherein the first element layer includes a second circuit,
wherein the second element layer includes a third circuit,
wherein the first circuit includes a driver circuit,
wherein the driver circuit includes a first transistor,
wherein the second circuit includes a second transistor,
wherein the third circuit includes a memory cell,
wherein the memory cell includes a third transistor and a first capacitor,
wherein a plurality of stacked blocks are stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate, the stacked blocks being constituted by the first element layer and the second element layer,
wherein the driver circuit included in the first circuit and the plurality of stacked blocks overlap with each other,
wherein each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate,
wherein the first wiring is provided in a hole penetrating the first element layer and the second element layer, and
wherein the first wirings of the plurality of stacked blocks are electrically connected to each other.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first circuit is configured to output a signal for driving the memory cell and data to be written to the memory cell to the first wiring and is configured to amplify data read from the memory cell into the first wiring.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second circuit is configured to amplify a potential of a second wiring electrically connected to the memory cell and transmit the amplified potential to the first wiring and is configured to transmit a potential of the first wiring to the second wiring.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the second transistor and the third transistor each include a semiconductor layer including a metal oxide in a channel formation region.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the metal oxide contains In, Ga, and Zn.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a first layer including the first capacitor is provided above a layer including the third transistor.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein a second layer including a second capacitor is stacked and provided on top of the first layer.