# US 12,015,011 B2 · Semiconductor device assemblies and systems with improved thermal performance and methods for making the same

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- Number: US 12,015,011 B2
- Document ID: US12015011B2
- Status: Granted
- Kind: B2
- Application number: 17/562,290
- Filed: 2021-12-27
- Published: 2022-04-21
- Granted: 2024-06-18
- Earliest claimed: 2020-06-24
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hyunsuk Chun; Xiaopeng Qu
- Web page: https://patentgrep.com/patent/US12015011B2

## CPC

- H10W 40/254: {Diamond}
- H10W 90/00: Package configurations
- H10W 40/25: characterised by their materials
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 40/226: {characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461)}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor device assemblies are provided with one or more layers of thermally conductive material disposed between adjacent semiconductor dies in a vertical stack. The thermally conductive material can be configured to conduct heat generated by one or more of the semiconductor dies in laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), or via adhering a film comprising the layer of thermally conductive material to one or more of the semiconductor dies.

## Claims

### Claim 1

A semiconductor device assembly, comprising:
a first semiconductor device;
a second semiconductor device disposed over the first semiconductor device along a vertical direction; and
a layer of thermally conductive material disposed between the first and second semiconductor devices, the layer of thermally conductive material configured to thermally conduct heat from between the first and second semiconductor devices outward in a lateral direction perpendicular to the vertical direction.

### Claim 2 (depends on 1)

The semiconductor device assembly of claim 1, wherein the layer of thermally conductive material is directly in contact with a back side of the second semiconductor device.

### Claim 3 (depends on 1)

The semiconductor device assembly of claim 1, wherein the layer of thermally conductive material is directly in contact with a front side of the first semiconductor device.

### Claim 4 (depends on 1)

The semiconductor device assembly of claim 1, wherein the layer of thermally conductive material is isolated from conductive interconnects disposed between and electrically connecting the first semiconductor device and the second semiconductor device.

### Claim 5 (depends on 1)

The semiconductor device assembly of claim 1, wherein the layer of thermally conductive material comprises one or more allotropes of carbon.

### Claim 6 (depends on 1)

The semiconductor device assembly of claim 1, wherein the layer of thermally conductive material comprises graphene, graphite, carbon nanotubes, or a combination thereof.

### Claim 7 (depends on 1)

The semiconductor device assembly of claim 1, wherein the layer of thermally conductive material has a thermal conductivity κ of greater than 500 W/(m° K).

### Claim 8 (depends on 1)

The semiconductor device assembly of claim 1, wherein the layer of thermally conductive material has a thickness of between 0.1 μm and 5 μm.

### Claim 9 (depends on 1)

The semiconductor device assembly of claim 1, wherein the layer of thermally conductive material has a plan area substantially similar to the first semiconductor device, the second semiconductor device, or both.

### Claim 10

A method of making a semiconductor device assembly, comprising:
providing a first semiconductor device;
disposing a second semiconductor device over the first semiconductor device along a vertical direction; and
disposing a layer of thermally conductive material between the first and second semiconductor devices, the layer of thermally conductive material configured to thermally conduct heat from between the first and second semiconductor devices outward in a lateral direction perpendicular to the vertical direction.

### Claim 11 (depends on 10)

The method of claim 10, wherein disposing the layer of thermally conductive material comprises depositing the layer of thermally conductive material over a back side of the second semiconductor device by sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

### Claim 12 (depends on 10)

The method of claim 10, wherein disposing the layer of thermally conductive material comprises adhering a film comprising the layer of thermally conductive material over a back side of the second semiconductor device.

### Claim 13 (depends on 10)

The method of claim 10, wherein the layer of thermally conductive material comprises graphene, graphite, carbon nanotubes, or a combination thereof.

### Claim 14 (depends on 10)

The method of claim 10, wherein the layer of thermally conductive material has a thermal conductivity κ of greater than 500 W/(m° K).

### Claim 15 (depends on 10)

The method of claim 10, wherein the layer of thermally conductive material has a thickness of between 0.1 μm and 5 μm.

### Claim 16 (depends on 10)

The method of claim 10, wherein disposing the layer of thermally conductive material comprises providing openings in the layer of thermally conductive material to electrically isolate interconnects disposed between the first semiconductor device and the second semiconductor device from the layer of thermally conductive material.

### Claim 17

A semiconductor device assembly, comprising:
a semiconductor device having a front side and a back side; and
a layer of thermally conductive material disposed immediately adjacent one of the front side or the back side, the layer of thermally conductive material configured to thermally conduct heat laterally outward toward one or more outer vertical surfaces of the semiconductor device assembly,
wherein the layer of thermally conductive material is disposed between the semiconductor device and either (i) a package substrate or (ii) an adjacent semiconductor device of the assembly.

### Claim 18 (depends on 17)

The semiconductor device assembly of claim 17, wherein the layer of thermally conductive material comprises graphene, graphite, carbon nanotubes, or a combination thereof.