# US 12,015,010 B2 · Vertically stacked semiconductor device including a hybrid bond contact junction circuit and methods of forming the same

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- Number: US 12,015,010 B2
- Document ID: US12015010B2
- Status: Granted
- Kind: B2
- Application number: 17/477,643
- Filed: 2021-09-17
- Published: 2022-10-06
- Granted: 2024-06-18
- Earliest claimed: 2021-03-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Jen-Yuan Chang; Chia-Ping Lai
- Web page: https://patentgrep.com/patent/US12015010B2

## CPC

- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 70/654: Top-view layouts
- H10W 72/01: {Manufacture or treatment}
- H10W 72/0198: {batch processes}
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first semiconductor die, a second semiconductor die including a side surface bonded to the first semiconductor die, such that the second semiconductor die is perpendicular to the first semiconductor die, and a junction circuit for connecting the first semiconductor die to the second semiconductor die.

## Claims

### Claim 1

A semiconductor device comprising:
a first semiconductor die including a first contact;
a second semiconductor die including a side surface bonded to the first semiconductor die such that the second semiconductor die is perpendicular to the first semiconductor die, wherein the side surface comprises:
a dielectric layer comprising at least one of interlayer dielectric or intermetal dielectric; and
a second contact in the dielectric layer; and
a junction circuit contacting the first contact and the second contact and configured to connect the first semiconductor die to the second semiconductor die.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor die comprises a first interface surface including the first contact,
wherein the second semiconductor die comprises a second interface surface formed in the side surface and including the second contact, and
wherein the junction circuit comprises a metal layer connecting the first contact to the second contact.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the second contact comprises at least one of a metal contact, a metal bonding pad, a metal trench, a metal barrier layer and a metal via.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, further comprising:
a bonding layer for bonding the second semiconductor die to the first semiconductor die, the junction circuit being formed in the bonding layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the junction circuit comprises a bonding redistribution layer (RDL) circuit that is formed in the bonding layer.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the junction circuit comprises a bonding pad that contacts the first contact in the first interface surface of the first semiconductor die.

### Claim 7

A junction circuit comprising:
a bonding trench comprising a first surface and a second surface opposite the first surface, and a first end and a second end opposite the first end;
a bonding pad formed on the first surface of the bonding trench and at the first end of the bonding trench, wherein the bonding pad is configured to electrically couple the junction circuit with a first die; and
a bonding via formed on the second surface of the bonding trench and at the second end of the bonding trench, wherein the bonding via is configured to electrically couple the junction circuit with a second die.

### Claim 8 (depends on 7)

The junction circuit of claim 7, wherein the bonding trench extends longitudinally in a first direction, and a length of the bonding trench in the first direction is greater than a length of the bonding pad in the first direction.

### Claim 9 (depends on 8)

The junction circuit of claim 8, wherein the length of the bonding trench in the first direction is greater than a length of the bonding via in the first direction.

### Claim 10 (depends on 9)

The junction circuit of claim 9, wherein the length of the bonding pad in the first direction is greater than the length of the bonding via in the first direction.

### Claim 11 (depends on 8)

The junction circuit of claim 8, wherein a width of the bonding trench in a second direction perpendicular to the first direction is less than a width of the bonding pad in the second direction.

### Claim 12 (depends on 11)

The junction circuit of claim 11, wherein the width of the bonding trench in the second direction is greater than a width of the bonding via in the second direction.

### Claim 13 (depends on 12)

The junction circuit of claim 12, wherein the width of the bonding pad in the second direction is greater than the width of the bonding via in the second direction.

### Claim 14 (depends on 10)

The junction circuit of claim 10, wherein a thickness of the bonding trench in a third direction perpendicular to the first direction and the second direction is substantially the same as a thickness of the bonding pad in the third direction.

### Claim 15 (depends on 14)

The junction circuit of claim 14, wherein the thickness of the bonding trench in the third direction is substantially the same as a thickness of the bonding via in the third direction.

### Claim 16 (depends on 15)

The junction circuit of claim 15, wherein the thickness of the bonding pad in the third direction is substantially the same as the thickness of the bonding via in the third direction.

### Claim 17 (depends on 14)

The junction circuit of claim 14, wherein the bonding via comprises a substantially circular cross-section in a first plane, and each of the bonding trench and bonding pad comprises a substantially rectangular cross-section in the first plane.

### Claim 18 (depends on 7)

The junction circuit of claim 7, wherein each of the bonding trench, bonding pad and bonding via comprise at least one of copper, a copper alloy, aluminum and an aluminum alloy.

### Claim 19 (depends on 7)

The junction circuit of claim 7, wherein the bonding trench, bonding pad and bonding via comprise metal wiring layers of a bonding redistribution layer (RDL) circuit.

### Claim 20

A method of making a semiconductor device, comprising:
forming a first semiconductor die including a first contact;
forming a second semiconductor die and forming a bonding layer on a side surface of the second semiconductor die, wherein the side surface includes:
a dielectric layer comprising at least one of interlayer dielectric or intermetal dielectric; and
a second contact in the dielectric layer;
forming a junction circuit in the bonding layer; and
bonding the bonding layer to the first semiconductor die such that the second semiconductor die is perpendicular to the first semiconductor die, and the junction circuit contacts the second contact in the dielectric layer of the side surface and connects the first semiconductor die to the second semiconductor die.