# US 12,015,009 B2 · Stacked semiconductor die architecture with multiple layers of disaggregation

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- Number: US 12,015,009 B2
- Document ID: US12015009B2
- Status: Granted
- Kind: B2
- Application number: 18/080,610
- Filed: 2022-12-13
- Published: 2023-04-06
- Granted: 2024-06-18
- Earliest claimed: 2022-12-13
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Edward Burton
- Web page: https://patentgrep.com/patent/US12015009B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/682: {comprising holes having chips therein}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

## Claims

### Claim 1

A stacked semiconductor architecture for a semiconductor package, comprising:
a first base die and a second base die; and
a layer on the first base die and the second base die, the layer including a first plurality of dies entirely within a footprint of the first base die and a second plurality of dies within a footprint of the second base die, wherein the layer electrically couples the first base die to the second base die with first interconnect structures, and wherein one or more second interconnect structures couple one or more of the first plurality of dies or the second plurality of dies and one or more of the first base die or the second base die, the one or more second interconnect structures laterally adjacent to the first interconnect structures.

### Claim 2 (depends on 1)

The stacked semiconductor architecture of claim 1, wherein the layer has a surface area that exceeds a total surface area of the first base die and the second base die.

### Claim 3 (depends on 1)

The stacked semiconductor architecture of claim 1, wherein the first base die and the second base die comprise one or more of:
(i) at least one monolithic base die; and
(ii) at least one disaggregated base die.

### Claim 4 (depends on 1)

The stacked semiconductor architecture of claim 1, wherein top sides of the first plurality of dies or the second plurality of in the layer are co-planar with a top side of the layer.

### Claim 5 (depends on 1)

The stacked semiconductor architecture of claim 1, wherein at least one of the first plurality of dies or the second plurality of dies in the layer is a memory die.

### Claim 6

A method of forming a stacked semiconductor architecture for a semiconductor package, comprising:
disposing a layer on a first base die and a second base die, the layer including a first plurality of dies entirely within a footprint of the first base die and a second plurality of dies entirely within a footprint of the second base die, wherein the layer electrically couples the first base die to the second base die with first interconnect structures, and wherein one or more second interconnect structures couple one or more of the first plurality of dies or the second plurality of dies and one or more of the first base die or the second base die to each other, the one or more second interconnect structures laterally adjacent to the first interconnect structures.

### Claim 7 (depends on 6)

The method of claim 6, wherein the layer has a surface area that exceeds a total surface area of the first base die and the second base die.

### Claim 8 (depends on 6)

The method of claim 6, wherein the first base die and the second base die comprise one or more of:
(i) at least one monolithic base die; and
(ii) at least one disaggregated base die.

### Claim 9 (depends on 6)

The method of claim 6, wherein top sides of the first plurality of dies and the second plurality of dies in the layer are co-planar with a top side of the layer.

### Claim 10 (depends on 6)

The method of claim 6, wherein at least one of the first plurality of dies or the second plurality of dies in the layer is a memory die.

### Claim 11 (depends on 6)

The method of claim 6, further comprising:
forming cavities in the layer; and
placing the first plurality of dies and the second plurality of dies in the cavities.

### Claim 12 (depends on 11)

The method of claim 11, further comprising bonding the first plurality of dies and the second plurality of dies to the layer.

### Claim 13 (depends on 11)

The method of claim 11, further comprising planarizing a top side of the layer and at least one top side of the first plurality of dies and the second plurality of dies in the layer.

### Claim 14 (depends on 6)

The method of claim 6, further comprising, for each of the first base die and the second base die, forming one or more microbumps on a top side of the first base die or the second base die.