# US 12,015,008 B2 · Wafer bonding method

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- Number: US 12,015,008 B2
- Document ID: US12015008B2
- Status: Granted
- Kind: B2
- Application number: 17/869,977
- Filed: 2022-07-21
- Published: 2022-11-17
- Granted: 2024-06-18
- Earliest claimed: 2020-03-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yung-Chi Lin; Tsang-Jiuh Wu; Wen-Chih Chiou; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US12015008B2

## CPC

- B23K 26/362: Laser etching
- H10P 50/267: {using plasmas}
- H10P 50/282: {of inorganic materials}
- H10P 50/283: {by chemical means}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 72/019: {of bond pads}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 72/0198: {batch processes}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 80/033: {by chemical means, e.g. etching}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/333: {Compression bonding}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/792: {between multiple chips}
- B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

## Claims

### Claim 1

A method comprising:
obtaining a first wafer comprising a first semiconductor substrate, a first dielectric layer, and first die connectors;
removing a first portion of the first dielectric layer in an edge region of the first wafer with a first trim process, the first trim process removing the first dielectric layer at a faster rate than the first semiconductor substrate;
removing a second portion of the first semiconductor substrate in the edge region of the first wafer with a second trim process, the second trim process removing the first semiconductor substrate at a faster rate than the first dielectric layer; and
bonding a second wafer to the first wafer, the second wafer comprising a second semiconductor substrate, a second dielectric layer, and second die connectors, the second dielectric layer bonded to the first dielectric layer with dielectric-to-dielectric bonds, the second die connectors bonded to the first die connectors with metal-to-metal bonds.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first trim process removes the first portion of the first dielectric layer along a first direction, and the second trim process removes the second portion of the first semiconductor substrate along a second direction, the first direction different from the second direction.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first direction forms an obtuse angle with the second direction, the second direction being perpendicular to an active surface of the first semiconductor substrate.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first trim process is a chemical etching process and the second trim process is a sawing process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first trim process is a chemical etching process and the second trim process is a chemical or ablative etching process.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first trim process is an ablative etching process and the second trim process is a sawing process.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first trim process is an ablative etching process and the second trim process is a chemical or ablative etching process.

### Claim 8 (depends on 1)

The method of claim 1 further comprising:
thinning the first semiconductor substrate to expose conductive vias of the first wafer and to remove a third portion of the first semiconductor substrate in the edge region of the first wafer.

### Claim 9 (depends on 8)

The method of claim 8 further comprising:
obtaining a third wafer comprising a third semiconductor substrate, a third dielectric layer, and third die connectors; and
bonding the third wafer to the first wafer, the third dielectric layer bonded to the first semiconductor substrate with dielectric-to-dielectric bonds, the third die connectors bonded to the conductive vias with metal-to-metal bonds.

### Claim 10 (depends on 1)

The method of claim 1, wherein after the first trim process, the first dielectric layer has a reentrant profile shape.

### Claim 11

A method comprising:
obtaining a first wafer comprising a semiconductor substrate and a dielectric layer;
removing edge regions of the dielectric layer with an etching process while a mask covers center regions of the dielectric layer, the etching process removing the edge regions of the dielectric layer along a first direction;
removing edge regions of the semiconductor substrate with a sawing process, the sawing process removing the edge regions of the semiconductor substrate along a second direction, second direction different from the first direction; and
bonding a second wafer to the first wafer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first direction forms an obtuse angle with the second direction, the second direction being perpendicular to an active surface of the semiconductor substrate.

### Claim 13 (depends on 11)

The method of claim 11, wherein after removing the edge regions of the dielectric layer, a width of the dielectric layer decreases continually in a direction extending away from an active surface of the semiconductor substrate.

### Claim 14

A structure comprising:
a first wafer comprising a first semiconductor substrate, a first dielectric layer, and first die connectors, a sidewall of the first dielectric layer forming an obtuse angle with a sidewall of the first semiconductor substrate; and
a second wafer comprising a second semiconductor substrate, a second dielectric layer, and second die connectors, the second dielectric layer bonded to the first dielectric layer with dielectric-to-dielectric bonds, the second die connectors bonded to the first die connectors with metal-to-metal bonds, a sidewall of the second dielectric layer being laterally offset from the sidewall of the first dielectric layer.

### Claim 15 (depends on 14)

The structure of claim 14, wherein a sidewall of the second semiconductor substrate is laterally offset from the sidewall of the first semiconductor substrate.

### Claim 16 (depends on 14)

The structure of claim 14, wherein the sidewall of the first semiconductor substrate has a first portion and a second portion, the first portion connecting the second portion to an active surface of the first semiconductor substrate, the first portion forming the obtuse angle with the second portion.

### Claim 17 (depends on 14)

The structure of claim 14, wherein the sidewall of the first semiconductor substrate forms a right angle with an active surface of the first semiconductor substrate.

### Claim 18 (depends on 14)

The structure of claim 14, wherein the sidewall of the first semiconductor substrate forms an acute angle with an active surface of the first semiconductor substrate.

### Claim 19 (depends on 14)

The structure of claim 14, wherein the first wafer further comprises conductive vias extending through the first semiconductor substrate.

### Claim 20 (depends on 14)

The structure of claim 14, wherein a width of the first dielectric layer decreases continually in a direction extending away from an active surface of the first semiconductor substrate.