# US 12,015,006 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 12,015,006 B2
- Document ID: US12015006B2
- Status: Granted
- Kind: B2
- Application number: 17/688,992
- Filed: 2022-03-08
- Published: 2022-09-29
- Granted: 2024-06-18
- Earliest claimed: 2021-03-23
- Assignees: Denso Corporation; Toyota Jidosha Kabushiki Kaisha; MIRISE Technologies Corporation
- Applicants: Denso Corporation; Toyota Jidosha Kabushiki Kaisha; MIRISE Technologies Corporation
- Inventors: Shohei Nagai
- Web page: https://patentgrep.com/patent/US12015006B2

## CPC

- H10W 72/30: Die-attach connectors
- H10W 72/073: {of die-attach connectors}
- H10W 72/01365: {Thermally treating (reflowing H10W72/01357)}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/07152: {Means for cooling}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07334: {Using a reflow oven}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/735: {between a chip and a laterally-adjacent insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a semiconductor element and a tin-based solder layer. The semiconductor element faces the substrate in a normal direction of the substrate. The normal direction corresponds to a normal line of the substrate. The tin-based solder layer joins the semiconductor element to the substrate. The tin-based solder layer a central portion and a peripheral portion surrounding the central portion. The tin-based solder layer has a tin crystal with a C-axis at each of the central portion and the peripheral portion. The C-axis at the central portion intersects the normal line at an angle larger than 45 degrees with respect to the normal line. The C-axis at the peripheral portion either intersects the normal line at an angle smaller than or equal to 45 degrees with respect to the normal line, or is parallel to the normal line.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a semiconductor element configured to face the substrate in a direction normal to the substrate, the direction being a normal direction of the substrate and corresponding to a normal line of the substrate; and
a tin-based solder layer configured to join the semiconductor element to the substrate,
wherein the tin-based solder layer includes a central portion and a peripheral portion surrounding the central portion in a view of the normal direction,
wherein the tin-based solder layer has a tin crystal with a C-axis, and the C-axis is at each of the central portion and the peripheral portion,
wherein the C-axis at the central portion intersects the normal line at an angle larger than 45 degrees with respect to the normal line, and
wherein the C-axis at the peripheral portion either intersects the normal line at an angle smaller than or equal to 45 degrees with respect to the normal line, or is parallel to the normal line.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the C-axis is orthogonal to the normal line at the central portion.