# US 12,015,004 B2 · Hybrid device assemblies and method of fabrication

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- Number: US 12,015,004 B2
- Document ID: US12015004B2
- Status: Granted
- Kind: B2
- Application number: 18/359,425
- Filed: 2023-07-26
- Published: 2023-11-16
- Granted: 2024-06-18
- Earliest claimed: 2020-10-22
- Assignees: NXP USA, Inc.
- Applicants: NXP USA, Inc.
- Inventors: Li Li; Lakshminarayan Viswanathan; Jeffrey Kevin Jones
- Web page: https://patentgrep.com/patent/US12015004B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04)
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10D 62/117: {Shapes of semiconductor bodies}
- H10W 40/10: Arrangements for heating
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 44/234: {Arrangements for impedance matching}
- H10W 44/248: {for antennas}
- H10W 44/251: {for monolithic microwave integrated circuits [MMIC]}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 70/682: {comprising holes having chips therein}
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/753: {between laterally-adjacent chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

## Claims

### Claim 1

A device assembly comprising:
a functional semiconductor substrate having a first surface and a second surface opposing the first surface, the functional semiconductor substrate having at least a first electronic component integrally formed therein from a volume of semiconductor material that is a portion of the functional semiconductor substrate;
an opening in the first surface of the functional semiconductor substrate that defines a cavity that extends toward the second surface functional semiconductor substrate; and
a semiconductor die disposed within the cavity.

### Claim 2 (depends on 1)

The device assembly of claim 1, further comprising:
a conductive structure disposed at the second surface of the functional semiconductor substrate;
wherein the conductive structure is electrically or thermally conductive and coupled to the second surface of the functional semiconductor substrate.

### Claim 3 (depends on 2)

The device assembly of claim 2, wherein the semiconductor die is coupled to the conductive structure by a metallurgical die attachment material disposed between the semiconductor die and the conductive structure.

### Claim 4 (depends on 3)

The device assembly of claim 3, wherein the metallurgical die attachment material is a sintered die attach material.

### Claim 5 (depends on 2)

The device assembly of claim 2, wherein the semiconductor die is coupled to the conductive structure via an electrically-conductive adhesive material.

### Claim 6 (depends on 2)

The device assembly of claim 2 wherein the conductive structure forms a bottom surface of the cavity and the semiconductor die is coupled to bottom surface of the cavity.

### Claim 7 (depends on 2)

The device assembly of claim 2,
wherein the cavity has a bottom surface formed by a portion of the functional semiconductor substrate between the first surface of the functional semiconductor substrate and the second surface of the functional semiconductor substrate.

### Claim 8 (depends on 7)

The device assembly of claim 7,
wherein the bottom surface of the cavity includes an opening that passes through the second surface of the functional semiconductor substrate; and
wherein the semiconductor die is coupled to the conductive structure via the opening in the bottom surface of the cavity.

### Claim 9 (depends on 8)

The device assembly of claim 8,
wherein a portion of the conductive structure extends within the opening in the bottom surface of the cavity.

### Claim 10 (depends on 8)

The device assembly of claim 8,
wherein the semiconductor die is coupled to the conductive structure via a metallurgical die attachment material disposed between the semiconductor die and the conductive structure within the opening in the bottom surface of the cavity.

### Claim 11 (depends on 1)

The device assembly of claim 1, wherein the semiconductor is secured within the cavity by a dielectric material disposed between the semiconductor die and a vertical wall of the cavity that surrounds the semiconductor die.

### Claim 12

A device assembly comprising:
a functional semiconductor substrate having a first surface and a second surface opposing the first surface, the functional semiconductor substrate having at least a first electronic component integrally formed therein from a volume of semiconductor material that is a portion of the functional semiconductor substrate;
an opening in the first surface of the functional semiconductor substrate that defines a cavity that extends toward the second surface functional semiconductor substrate;
a semiconductor die disposed within the cavity; and
a build-up structure formed across the first surface of the functional semiconductor substrate or the second surface of the functional semiconductor substrate, the build-up structure including at least one layer of electrically insulating material surrounding an electrically conductive contact coupled to a surface of the semiconductor die.

### Claim 13 (depends on 12)

The device assembly of claim 12,
wherein the build-up structure is formed on the first surface of the functional semiconductor substrate and a top surface of the semiconductor die; and
wherein the electrically conductive contact is disposed on the top surface of the semiconductor die.

### Claim 14 (depends on 13)

The device assembly of claim 13, wherein the electrically conductive contact is a metallic pillar.

### Claim 15 (depends on 14)

The device of assembly of claim 14 further comprising an additional electrically conductive contact comprising a metallic pillar disposed on a top surface of the functional semiconductor substrate and surrounded by the build-up structure.

### Claim 16 (depends on 14)

The device of assembly of claim 14,
wherein the metallic pillar is a first metallic pillar; and
wherein the device assembly further comprises an additional electrically conductive contact comprising a second metallic pillar disposed on a top surface of the functional semiconductor substrate and surrounded by the build-up structure.

### Claim 17 (depends on 16)

The device of assembly of claim 16,
wherein the build-up structure has a bottom surface that contacts the top surface of the semiconductor die and the top surface of the functional semiconductor substrate;
wherein the build-up structure has a top surface opposite the bottom surface of the build-up structure; and
wherein the first metallic pillar and the second metallic pillar are exposed at the top surface of the build-up structure.

### Claim 18 (depends on 12)

The device of assembly of claim 12,
wherein the build-up structure includes an electrical interconnect coupled to the electrically conductive contact of the semiconductor die, the electrical interconnect being formed by at least one layer of patterned electrically conductive material surrounded by the electrically insulating material of the build-up structure.

### Claim 19 (depends on 12)

The device assembly of claim 12,
wherein the build-up structure is formed on the second surface of the functional semiconductor substrate and a bottom surface of the semiconductor die disposed within the cavity opposite the first surface of the functional semiconductor substrate and adjacent to the second surface of the functional semiconductor substrate; and
wherein the electrically conductive contact is disposed on the bottom surface of the semiconductor die.

### Claim 20 (depends on 19)

The device assembly of claim 19, wherein the build-up structure forms a bottom surface of the cavity and the electrically conductive contact of the semiconductor die is coupled to the electrically conductive patterned material of the build-up structure at the bottom surface of the cavity.

### Claim 21 (depends on 19)

The device assembly of claim 19,
wherein the cavity has a bottom surface formed by a portion of the functional semiconductor substrate and the bottom surface of the cavity includes an opening that passes though second surface of the functional semiconductor substrate; and
wherein the electrically conductive element of the semiconductor die is coupled to the electrically conductive patterned material of the build-up structure within the opening in the bottom surface of the cavity.

### Claim 22

A device assembly comprising:
a functional semiconductor substrate having a first surface and a second surface opposing the first surface, the functional semiconductor substrate having at least a first electronic component integrally formed therein from a volume of semiconductor material that is a portion of the functional semiconductor substrate;
an opening in the first surface of the functional semiconductor substrate that defines a cavity that extends toward the second surface functional semiconductor substrate; and
a semiconductor die placed within the cavity;
wherein the semiconductor die comprises a compound semiconductor transistor device; and
wherein the first electronic component is coupled to the compound semiconductor transistor device.

### Claim 23 (depends on 22)

The device assembly of claim 22, wherein the first electronic component is part of an impedance matching circuit electrically coupled to an input node or an output node of the compound semiconductor transistor device.

### Claim 24 (depends on 22)

The device assembly of claim 22 wherein the compound semiconductor transistor device is configured to generate or receive electrical signals in a radio-frequency, microwave, or millimeter-wave frequency range.

### Claim 25 (depends on 22)

The device assembly of claim 22, wherein the first electronic component is formed within a volume of an elemental semiconductor material.

### Claim 26 (depends on 22)

The device assembly of claim 22, further comprising:
a build-up structure formed across the first surface of the functional semiconductor substrate or the second surface of the functional semiconductor substrate, the build-up structure including an electrical interconnect coupled to an electrically conductive element on a surface of the semiconductor die, the electrical interconnect being formed by at least one layer of patterned electrically conductive material surrounded by electrically insulating material;
wherein the first electronic component is electrically coupled to the compound semiconductor transistor device via the electrical interconnect of the build-up structure.

### Claim 27

A method comprising:
receiving a functional semiconductor substrate having a first surface and a second surface opposing the first surface, the functional semiconductor substrate having at least a first electronic component integrally formed therein from a volume of semiconductor material that is a portion of the functional semiconductor substrate;
forming an opening in the first surface of the functional semiconductor substrate that defines a cavity that extends toward the second surface functional semiconductor substrate; and
disposing a semiconductor die within the cavity.

### Claim 28 (depends on 27)

The method of claim 27,
wherein a conductive structure is disposed at the second surface of the functional semiconductor substrate; and
wherein the conductive structure is electrically or thermally conductive and coupled to the second surface of the functional semiconductor substrate.

### Claim 29 (depends on 28)

The method of claim 28, further comprising coupling the semiconductor die to the conductive structure using a sintered metallurgical die attachment material disposed between the semiconductor die and the conductive structure.

### Claim 30 (depends on 28)

The method of claim 28 wherein the conductive structure forms at least a portion of a bottom surface of the cavity.

### Claim 31 (depends on 27)

The method of claim 27, further comprising:
forming a build-up structure across the first surface of the functional semiconductor substrate or the second surface of the functional semiconductor substrate, the build-up structure including an electrical interconnect coupled to an electrically conductive contact on a surface of the semiconductor die, the electrical interconnect being formed by at least one layer of patterned electrically conductive material surrounded by electrically insulating material.

### Claim 32 (depends on 31)

The method of claim 31,
wherein the first electronic device is formed within a volume of an elemental semiconductor material;
wherein the semiconductor die includes a compound semiconductor transistor device; and
wherein the method further comprises electrically coupling the first electronic component to the compound semiconductor transistor device via the electrical interconnect of the build-up structure.