# US 12,015,003 B2 · High density interconnection and wiring layers, package structures, and integration methods

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- Number: US 12,015,003 B2
- Document ID: US12015003B2
- Status: Granted
- Kind: B2
- Application number: 17/488,968
- Filed: 2021-09-29
- Published: 2023-03-30
- Granted: 2024-06-18
- Earliest claimed: 2021-09-29
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: John Knickerbocker; Mukta Ghate Farooq; Katsuyuki Sakuma
- Web page: https://patentgrep.com/patent/US12015003B2

## CPC

- H01P 3/003: {Coplanar lines}
- H10W 90/00: Package configurations
- H01P 11/003: {Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04)
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 44/209: {Vertical interconnections, e.g. vias}
- H10W 44/216: {Waveguides, e.g. strip lines}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/801: {Interconnections on sidewalls of containers}
- H10W 76/167: {the container walls comprising an aperture, e.g. for pressure control}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.

## Claims

### Claim 1

An interconnect for a semiconductor device, the interconnect comprising:
a laminate substrate;
a first plurality of electrical devices in or on a surface of the laminate substrate;
a redistribution layer having a surface disposed on the surface of the laminate substrate using a handle layer;
a second plurality of electrical devices in or on the surface of the redistribution layer; and
a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices;
wherein the surface of the laminate substrate and the surface of the redistribution layer are parallel to each other such that the first plurality of electrical devices and the second plurality of electrical devices are interconnected upon removal of the handle layer to form a dielectric structure and a conductor structure.

### Claim 2 (depends on 1)

The interconnect of claim 1, wherein the transmission lines comprise metal posts extending from the first plurality of electrical devices.

### Claim 3 (depends on 1)

The interconnect of claim 1, wherein the transmission lines comprises vias extending from the first plurality of electrical devices.

### Claim 4 (depends on 1)

The interconnect of claim 1, further comprising an adhesive dielectric layer between the redistribution layer and the laminate substrate.

### Claim 5 (depends on 1)

The interconnect of claim 1, wherein the first plurality of electrical devices and the second plurality of electrical devices are connected using a solder interconnect.

### Claim 6 (depends on 1)

The interconnect of claim 1, wherein the surface of the laminate substrate and the surface of the redistribution layer are adhesively joined.

### Claim 7

A method of forming a semiconductor device, the method comprising:
forming a coreless laminate substrate;
forming a first plurality of electrical devices in or on a surface of the laminate substrate;
forming interconnection ports at the first plurality of electrical devices;
forming a redistribution layer on a handle layer, the redistribution layer having a second plurality of electrical devices on or in a surface of the redistribution layer;
connecting the redistribution layer to the laminate substrate using the handle layer such that the second plurality of electrical devices is interconnected to the first plurality of electrical devices through the interconnection ports;
wherein when the redistribution layer is connected to the laminate substrate, the surface of the laminate substrate and the surface of the redistribution layer are parallel to each other.

### Claim 8 (depends on 7)

The method of claim 7, wherein the coreless laminate substrate is formed by sequential deposition of layers to form a board.

### Claim 9 (depends on 7)

The method of claim 7, wherein forming interconnection ports at the first plurality of electrical devices comprises forming metal posts at the first plurality of electrical devices.

### Claim 10 (depends on 7)

The method of claim 7, wherein forming interconnection ports at the first plurality of electrical devices comprises forming vias at the first plurality of electrical devices.

### Claim 11 (depends on 7)

The method of claim 7, wherein connecting the redistribution layer to the laminate substrate comprises applying flowable adhesive dielectric material between the redistribution layer and the laminate substrate.

### Claim 12 (depends on 7)

The method of claim 7, further comprising applying an adhesive between the surface of the laminate substrate and the surface of the redistribution layer.

### Claim 13

A method for fabricating an interconnect for a semiconductor device, the method comprising:
forming a multi-layer base substrate;
forming a first plurality of electrical and/or optical semiconductor devices in or on a surface of the multi-layer base substrate;
forming first ends of interconnection ports at the first plurality of electrical and/or optical semiconductor devices;
forming a second plurality of electrical and/or optical semiconductor devices at second ends of the interconnection ports distal from the first ends;
forming a redistribution layer on a handle layer, the redistribution layer having a third plurality of electrical and/or optical semiconductor devices in or on the redistribution layer;
connecting the redistribution layer to the handle layer;
disposing the handle layer onto the second plurality of electrical and/or optical semiconductor devices; and
removing the handle layer;
wherein the surface of the multi-layer base substrate and the surface of the redistribution layer are parallel to each other to form dielectric and conductor structures.

### Claim 14 (depends on 13)

The method of claim 13, wherein the multi-layer base substrate is formed by sequential deposition of layers to form a board.

### Claim 15 (depends on 13)

The method of claim 13, wherein the multi-layer base substrate is famed from one or more dielectric materials selected from glass and organic polymers and from one or more electrical conductors and/or optical conductors selected from copper, nickel, gold, tungsten, titanium, tantalum, solder, silicon, and silicon nitride.

### Claim 16 (depends on 13)

The method of claim 13, wherein the multi-layer base substrate comprises electrical and/or optical interconnections.

### Claim 17 (depends on 13)

The method of claim 13, wherein the interconnection ports are metal posts or vias.

### Claim 18 (depends on 13)

The method of claim 13, further comprising disposing a lid on the redistribution layer opposite to the handle layer.

### Claim 19 (depends on 13)

The method of claim 13, wherein the surface of the multi-layer base substrate and the surface of the redistribution layer are adhesively joined.