# US 12,015,002 B2 · Chip structure and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,015,002 B2 - Document ID: US12015002B2 - Status: Granted - Kind: B2 - Application number: 17/460,906 - Filed: 2021-08-30 - Published: 2023-03-02 - Granted: 2024-06-18 - Earliest claimed: 2021-08-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Hui-Min Huang; Ming-Da Cheng; Wei-Hung Lin; Chang-Jung Hsueh; Kai-Jun Zhan; Yung-Sheng Lin - Web page: https://patentgrep.com/patent/US12015002B2 ## CPC - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/654: Top-view layouts - H10W 70/68: Shapes or dispositions thereof - H10W 72/07252: {changes in structures or sizes} - H10W 72/07253: {changes in shapes} - H10W 72/221: {Structures or relative sizes} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/224: {Bumps having multiple side-by-side cores} - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar. ## Claims ### Claim 1 A chip structure, comprising: a substrate; a first conductive line over the substrate; an insulating layer over the substrate and the first conductive line; a conductive pillar over the insulating layer, wherein the first conductive line is longer than the conductive pillar in a first top view of the first conductive line and the conductive pillar, the conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer, the protruding locking portion has an end surface facing the substrate, a first portion of the insulating layer is between the end surface and the substrate, the conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, and the first conductive line extends across the first sidewall and the second sidewall; and a solder bump on the conductive pillar, wherein the solder bump is in contact with the conductive pillar. ### Claim 2 (depends on 1) The chip structure as claimed in claim 1, further comprising: a second conductive line between the substrate and the conductive pillar, wherein a first top surface of the first conductive line is substantially level with a second top surface of the second conductive line, and the protruding locking portion of the conductive pillar is between the first conductive line and the second conductive line in a second top view of the conductive pillar, the first conductive line, and the second conductive line. ### Claim 3 (depends on 2) The chip structure as claimed in claim 2, wherein there is no conductive line between the first conductive line and the second conductive line. ### Claim 4 (depends on 1) The chip structure as claimed in claim 1, wherein the protruding locking portion has a strip shape in the first top view of the conductive pillar and the first conductive line. ### Claim 5 (depends on 4) The chip structure as claimed in claim 4, wherein a first longitudinal axis of the protruding locking portion is substantially parallel to a second portion of the first conductive line under the conductive pillar in the first top view of the conductive pillar and the first conductive line. ### Claim 6 (depends on 5) The chip structure as claimed in claim 5, wherein the protruding connecting portion has a strip shape, and a second longitudinal axis of the protruding connecting portion is substantially parallel to the first longitudinal axis of the protruding locking portion in the first top view of the conductive pillar and the first conductive line. ### Claim 7 (depends on 1) The chip structure as claimed in claim 1, wherein the insulating layer is a single-layered structure. ### Claim 8 A chip structure, comprising: a substrate; a conductive line over the substrate; an insulating layer over the substrate and the conductive line; a conductive pillar over the insulating layer covering the conductive line, wherein the conductive line is longer than the conductive pillar in a first top view of the conductive line and the conductive pillar, the conductive pillar is formed in one piece, the conductive pillar has an upper surface having a first part and a second part, the first part is over the conductive line, the second part is not over the conductive line, a first distance between the first part and the substrate is greater than a second distance between the second part and the substrate, and the conductive pillar is in direct contact with the conductive line; and a solder bump on the conductive pillar, wherein the solder bump is in contact with the conductive pillar. ### Claim 9 (depends on 8) The chip structure as claimed in claim 8, wherein the conductive pillar having the first part of the upper surface and the conductive pillar having the second part of the upper surface have a substantially same thickness. ### Claim 10 (depends on 8) The chip structure as claimed in claim 8, wherein the second part of the upper surface has a substantially D shape, a substantially L shape, or a strip shape. ### Claim 11 (depends on 8) The chip structure as claimed in claim 8, wherein the conductive pillar further has a protruding connecting portion and a protruding locking portion, the protruding connecting portion protrudes from the lower surface of the conductive pillar and passes through the insulating layer and is in direct contact with the conductive line, the protruding locking portion protrudes from the lower surface of the conductive pillar and is spaced apart from the conductive line, and the protruding locking portion is longer than the protruding connecting portion in a second top view of the protruding locking portion and the protruding connecting portion. ### Claim 12 (depends on 11) The chip structure as claimed in claim 11, wherein the protruding locking portion is thinner than the protruding connecting portion. ### Claim 13 (depends on 11) The chip structure as claimed in claim 11, wherein a first bottom surface of the protruding connecting portion is closer to the substrate than a second bottom surface of the protruding locking portion. ### Claim 14 A method for forming a chip structure, comprising: forming a first conductive line over a substrate; forming an insulating layer over the substrate and the first conductive line, wherein the insulating layer has a first recess, and a first edge of the first conductive line is substantially parallel to a second edge of the first recess in a top view of the first conductive line and the insulating layer; forming a conductive pillar over the insulating layer covering the first conductive line, wherein the conductive pillar is formed in one piece, the conductive pillar has a protruding locking portion in the first recess, the protruding locking portion has a first sidewall, a second sidewall, and a flat end surface facing the substrate and between the first sidewall and the second sidewall, and a first portion of the insulating layer is between the flat end surface and the substrate; and forming a solder bump on the conductive pillar, wherein the solder bump is in contact with the conductive pillar. ### Claim 15 (depends on 14) The method for forming the chip structure as claimed in claim 14, wherein the insulating layer further has a through hole, the through hole exposes a second portion of the first conductive line, the conductive pillar further has a protruding connecting portion in the through hole, and the protruding connecting portion is in direct contact with the second portion of the first conductive line. ### Claim 16 (depends on 14) The method for forming the chip structure as claimed in claim 14, wherein a linewidth of a second portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. ### Claim 17 (depends on 14) The method for forming the chip structure as claimed in claim 14, further comprising: forming a second conductive line over the substrate while forming the first conductive line over the substrate, wherein the second conductive line is between the substrate and the conductive pillar, a first top surface of the first conductive line is substantially level with a second top surface of the second conductive line, and the protruding locking portion of the conductive pillar is between the first conductive line and the second conductive line in a top view of the conductive pillar, the first conductive line, and the second conductive line. ### Claim 18 (depends on 17) The method for forming the chip structure as claimed in claim 17, wherein there is no conductive line between the first conductive line and the second conductive line. ### Claim 19 (depends on 14) The method for forming the chip structure as claimed in claim 14, wherein the conductive pillar has an upper surface having a first part and a second part, the first part is over the first conductive line, the second part is not over the first conductive line, and a first distance between the first part and the substrate is greater than a second distance between the second part and the substrate. ### Claim 20 (depends on 19) The method for forming the chip structure as claimed in claim 19, wherein the second part of the upper surface is closer to an edge of the substrate than the first part of the upper surface.