# US 12,014,999 B2 · Integration and bonding of micro-devices into system substrate

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- Number: US 12,014,999 B2
- Document ID: US12014999B2
- Status: Granted
- Kind: B2
- Application number: 17/031,587
- Filed: 2020-09-24
- Published: 2021-01-21
- Granted: 2024-06-18
- Earliest claimed: 2017-11-14
- Assignees: VueReal Inc.
- Applicants: VueReal Inc.
- Inventors: Gholamreza Chaji; Bahareh Sadeghimakki
- Web page: https://patentgrep.com/patent/US12014999B2

## CPC

- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H03H 3/00: Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H10H 20/0364: {of interconnections}
- H10W 72/01351: {Changing the shapes of die-attach connectors}
- H10W 72/01353: {by etching}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core}
- H10W 72/324: {Die-attach connectors having multiple side-by-side cores}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/355: {of outermost layers of multilayered die-attach connectors, e.g. material of a coating}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

## Claims

### Claim 1

A method of electrically bonding a microdevice into a receiver substrate, the method comprising:
bonding at least a part of one surface of at least one bonding pad on a receiver substrate to at least a part of another surface of at least an optoelectronic microdevice on a donor substrate,
covering a gap between the at least one bonding pad and the at least one optoelectronic microdevice with a nanowire,
coating the nanowire with a bonding material to decrease a resistance of the nanowire, and
applying a current to the at least one boding pad to decrease the contact resistance.

### Claim 2 (depends on 1)

The method of claim 1, wherein the nanowire coating comprises of nanoparticles.

### Claim 3 (depends on 1)

The method of claim 1, wherein the nanowire coating is done by deposition of metal on the nanowire.

### Claim 4 (depends on 1)

The method of claim 1, wherein the nanowire coating is In, Ag or Sn.

### Claim 5 (depends on 1)

The method of claim 1, wherein the nanowire is a metal, a TOC or a carbon nanotube.

### Claim 6 (depends on 1)

The method of claim 1, wherein an electrical energy is applied to the nanowire to reduce the resistivity.

### Claim 7 (depends on 6)

The method of claim 6, wherein the electrical energy is applied as a pulsed voltage.

### Claim 8 (depends on 1)

The method of claim 1, wherein a bonding material enhances the eutectic bonding to form alloys with Ag nano-wires and lower the thermal input required for bonding.

### Claim 9 (depends on 1)

The method of claim 1, wherein the dc current is 400 mA applied constantly for 80 seconds.

### Claim 10 (depends on 1)

The method of claim 1, wherein the resistance is decreased greater at lower currents within a 25-800 mA range.

### Claim 11 (depends on 1)

The method of claim 1, wherein Indium and Tin bonding materials coated on the Ag nano-wires have an equivalent effect on resistance.

### Claim 12 (depends on 10)

The method of claim 10, a bilayer In/Tin coated Ag nano-wires further lower bare nano-wires resistance to half of its original value with lower currents.

### Claim 13 (depends on 12)

The method of claim 12, the coating of nanowires with bonding materials reinforces nanowires interconnections to a significant degree creating more current pathways after Joule heating, due to greater contact points from deposited metal regions, resulting in lower electrical resistance within the range.

### Claim 14 (depends on 1)

The method of claim 1, wherein a coating of Ag nano-wires with bonding material fills a gap between nano-joints and form alloys with Ag nano-wires and lowers a thermal input required to undergo a Joule-heating.

### Claim 15 (depends on 1)

The method of claim 1, wherein a pulse dc current is applied.

### Claim 16 (depends on 15)

The method of claim 15, wherein there is a logarithmic decrease in resistance of Ag nano-wires as a magnitude of applied current is increased.

### Claim 17 (depends on 15)

The method of claim 15, wherein a 25 Hz waveform, altering between an “on-time” and an “off-time” in one direction, results in a maximum decrease in resistance when compared to a standard DC current.

### Claim 18 (depends on 17)

The method of claim 17, wherein the “on-time” supplies sufficient energy to sinter nanowires.