# US 12,014,997 B2 · Dummy stacked structures surrounding TSVs and method forming the same

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- Number: US 12,014,997 B2
- Document ID: US12014997B2
- Status: Granted
- Kind: B2
- Application number: 17/464,903
- Filed: 2021-09-02
- Published: 2023-01-05
- Granted: 2024-06-18
- Earliest claimed: 2021-07-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Mingni Chang; Yun-Chin Tsou; Ching-Jing Wu; Shiou-Fan Chen; Ming-Yih Wang
- Web page: https://patentgrep.com/patent/US12014997B2

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/42: Vias, e.g. via plugs
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a plurality of low-k dielectric layers over a semiconductor substrate, forming a first plurality of dummy stacked structures extending into at least one of the plurality of low-k dielectric layers, forming a plurality of non-low-k dielectric layers over the plurality of low-k dielectric layers, and forming a second plurality of dummy stacked structures extending into the plurality of non-low-k dielectric layers. The second plurality of dummy stacked structures are over and connected to corresponding ones of the first plurality of dummy stacked structures. The method further includes etching the plurality of non-low-k dielectric layers, the plurality of low-k dielectric layers, and the semiconductor substrate to form a via opening. The via opening is encircled by the first plurality of dummy stacked structures and the second plurality of dummy stacked structures. The via opening is then filled to form a through-via.

## Claims

### Claim 1

A method comprising:
forming a plurality of low-k dielectric layers over a semiconductor substrate;
forming a first plurality of dummy stacked structures extending into at least one of the plurality of low-k dielectric layers;
forming a plurality of non-low-k dielectric layers over the plurality of low-k dielectric layers;
forming a second plurality of dummy stacked structures extending into the plurality of non-low-k dielectric layers, wherein the second plurality of dummy stacked structures are over and connected to corresponding ones of the first plurality of dummy stacked structures;
etching the plurality of non-low-k dielectric layers, the plurality of low-k dielectric layers, and the semiconductor substrate to form a via opening, wherein the via opening is encircled by the first plurality of dummy stacked structures and the second plurality of dummy stacked structures; and
filling the via opening to form a through-via.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first plurality of dummy stacked structures comprise a plurality of portions in one of the plurality of low-k dielectric layers, and the plurality of portions are disconnected from each other.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
forming an integrated circuit at a surface of the semiconductor substrate; and
forming a plurality of electrical connection structures electrically coupling to the integrated circuit, wherein the plurality of electrical connection structures are formed in same processes as the first plurality of dummy stacked structures and the second plurality of dummy stacked structures.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first plurality of dummy stacked structures and the second plurality of dummy stacked structures are electrically floating.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first plurality of dummy stacked structures and the second plurality of dummy stacked structures are spaced apart from the via opening by spacings smaller than about 1 μm.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first plurality of dummy stacked structures extend to the semiconductor substrate.

### Claim 7 (depends on 1)

The method of claim 1, wherein bottoms of the first plurality of dummy stacked structures are higher than, and are spaced apart from, the semiconductor substrate.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first plurality of dummy stacked structures form a plurality of rings, each fully encircling the via opening.

### Claim 9 (depends on 1)

The method of claim 1 further comprising performing a baking process on a respective wafer comprising the via opening.

### Claim 10

A method comprising:
forming a plurality of low-k dielectric layers over a semiconductor substrate;
forming a first plurality of dummy stacked structures extending into at least one of the plurality of low-k dielectric layers;
forming a plurality of non-low-k dielectric layers over the plurality of low-k dielectric layers;
forming a second plurality of dummy stacked structures extending into the plurality of non-low-k dielectric layers, wherein the second plurality of dummy stacked structures are over and connected to corresponding ones of the first plurality of dummy stacked structures, wherein the first plurality of dummy stacked structures comprise a plurality of portions in the at least one of the plurality of low-k dielectric layers, and the plurality of portions are disconnected from each other;
etching the plurality of non-low-k dielectric layers, the plurality of low-k dielectric layers, and the semiconductor substrate to form a via opening, wherein the via opening is encircled by the first plurality of dummy stacked structures and the second plurality of dummy stacked structures; and
filling the via opening to form a through-via.

### Claim 11 (depends on 10)

The method of claim 10 further comprising:
forming an integrated circuit at a surface of the semiconductor substrate; and
forming a plurality of electrical connection structures electrically coupling to the integrated circuit, wherein the plurality of electrical connection structures are formed in same processes as the first plurality of dummy stacked structures and the second plurality of dummy stacked structures.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first plurality of dummy stacked structures and the second plurality of dummy stacked structures are electrically floating.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first plurality of dummy stacked structures and the second plurality of dummy stacked structures are spaced apart from the via opening by spacings smaller than about 1 μm.

### Claim 14 (depends on 10)

The method of claim 10, wherein the first plurality of dummy stacked structures are electrically coupled to the semiconductor substrate.

### Claim 15 (depends on 10)

The method of claim 10, wherein the first plurality of dummy stacked structures are aligned to a plurality of rings, each fully encircling the via opening.

### Claim 16

A method comprising:
forming a plurality of low-k dielectric layers over a semiconductor substrate;
forming a first plurality of dummy stacked structures extending into at least one of the plurality of low-k dielectric layers;
forming a plurality of non-low-k dielectric layers over the plurality of low-k dielectric layers;
forming a second plurality of dummy stacked structures extending into the plurality of non-low-k dielectric layers, wherein the second plurality of dummy stacked structures are over and connected to corresponding ones of the first plurality of dummy stacked structures, wherein in a top view of the second plurality of dummy stacked structures, neighboring ones of the second plurality of dummy stacked structures are separated from each other by a substantially uniform spacing;
etching the plurality of non-low-k dielectric layers, the plurality of low-k dielectric layers, and the semiconductor substrate to form a via opening, wherein the via opening is encircled by the first plurality of dummy stacked structures and the second plurality of dummy stacked structures; and
filling the via opening to form a through-via, wherein in the top view, first ones of the second plurality of dummy stacked structures are aligned to a first ring that encircling the through-via.

### Claim 17 (depends on 16)

The method of claim 16, wherein in the top view, second ones of the second plurality of dummy stacked structures are aligned to a second ring that encircles the first ring.

### Claim 18 (depends on 16)

The method of claim 16, wherein the first plurality of dummy stacked structures and the second plurality of dummy stacked structures are electrically floating.

### Claim 19 (depends on 16)

The method of claim 16, wherein the first plurality of dummy stacked structures are electrically coupled to the semiconductor substrate.

### Claim 20 (depends on 16)

The method of claim 16, wherein bottoms of the first plurality of dummy stacked structures are higher than, and are spaced apart from, the semiconductor substrate.