# US 12,014,996 B2 · Moisture hermetic guard ring for semiconductor on insulator devices

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- Number: US 12,014,996 B2
- Document ID: US12014996B2
- Status: Granted
- Kind: B2
- Application number: 16/914,045
- Filed: 2020-06-26
- Published: 2021-12-30
- Granted: 2024-06-18
- Earliest claimed: 2020-06-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Mohammad Kabir; Conor P. Puls; Babita Dhayal; Han Li; Keith E. Zawadzki; Hannes Greve; Avyaya Jayanthinarasimham; Mukund Bapna; Doug B. Ingerly
- Web page: https://patentgrep.com/patent/US12014996B2

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 90/1906: {Preparing SOI wafers}
- H10P 90/1914: {using bonding}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10D 86/01: Manufacture or treatment
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

## Claims

### Claim 1

A device comprising:
a device layer adjacent to an interconnect layer, the device layer comprising a plurality of semiconductor devices and the interconnect layer comprising a plurality of metal interconnects;
a bonding layer on a support substrate and adjacent one of the interconnect layer or the device layer; and
a guard ring structure, wherein the guard ring structure laterally surrounds the semiconductor devices and the metal interconnects, extends through the bonding layer, the interconnect layer, and the device layer, and is in contact with the support substrate.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a second guard ring structure within the interconnect layer, wherein the second guard ring structure surrounds the metal interconnects and extends from a first surface of the interconnect layer and terminates at a first surface of the device layer, wherein the guard ring structure extends through the first surface of the interconnect layer, the first surface of the device layer, and a second surface of the device layer opposite the first surface of the device layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the bonding layer is on a first surface of the support substrate and the guard ring structure extends not less than 200 nm beyond the first surface into support substrate.

### Claim 4 (depends on 1)

The device of claim 1, wherein the bonding layer is adjacent the interconnect layer, the device further comprising:
a plurality of via structures within a perimeter of the guard ring structure, wherein each of the via structures extends through the bonding layer, the interconnect layer, and the device layer, and is in contact with the support substrate.

### Claim 5 (depends on 4)

The device of claim 4, wherein at least one of the plurality of via structures is to couple to a ground plane.

### Claim 6 (depends on 1)

The device of claim 1, wherein the guard ring structure comprises a barrier layer and a fill material within the barrier layer, the barrier layer comprising a metal and oxygen and the fill material comprising copper.

### Claim 7 (depends on 6)

The device of claim 6, wherein the guard ring structure further comprises a polymer liner, wherein the barrier layer is within the polymer liner.

### Claim 8 (depends on 1)

The device of claim 1, wherein the support substrate and the device layer comprise silicon and the bonding layer comprises silicon and oxygen.

### Claim 9 (depends on 1)

The device of claim 1, wherein the guard ring structure comprises a lateral width between sidewalls thereof of not less than 4 microns.

### Claim 10 (depends on 9)

The device of claim 9, wherein the guard ring structure defines a substantially rectangular or square perimeter around the semiconductor devices and the metal interconnects.

### Claim 11 (depends on 1)

The device of claim 1, wherein the guard ring structure is laterally surrounded by outer edges of the device layer, the interconnect layer, the bonding layer, and the support substrate.

### Claim 12 (depends on 1)

The device is claim 1, further comprising:
a heat exchanger thermally coupled to the support substrate.