# US 12,014,995 B2 · Warpage-reducing semiconductor structure and fabricating method of the same

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- Number: US 12,014,995 B2
- Document ID: US12014995B2
- Status: Granted
- Kind: B2
- Application number: 17/369,936
- Filed: 2021-07-07
- Published: 2022-12-08
- Granted: 2024-06-18
- Earliest claimed: 2021-06-07
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Da-Jun Lin; Chin-Chia Yang; Tai-Cheng Hou; Fu-Yu Tsai; Bin-Siang Tsai
- Web page: https://patentgrep.com/patent/US12014995B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6538: {by exposure to UV light}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10W 20/42: Vias, e.g. via plugs
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/635: {Through-vias}
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 74/01: Manufacture or treatment
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

## Claims

### Claim 1

A warpage-reducing semiconductor structure, comprising:
a wafer comprising a front side and a back side;
a plurality of semiconductor elements disposed at the front side, wherein the plurality of semiconductor elements comprise a plurality of first input/output (I/O) metal elements disposed at the front side, and the plurality of first I/O metal elements provide a first tensile stress to make the wafer bend toward the front side;
a silicon oxide layer directly contacting the back side;
a UV-transparent silicon nitride layer covering and contacting the silicon oxide layer, wherein a refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10, and the silicon oxide layer is sandwiched between the back side and the UV-transparent silicon nitride layer; and
a plurality of second I/O metal elements disposed at the back side, wherein the plurality of second I/O metal elements provide a second tensile stress to make the wafer bend toward the back side, the second tensile stress is smaller than the first tensile stress, the silicon oxide layer and the UV-transparent silicon nitride layer are disposed between the plurality of second I/O metal elements and the back side, and the silicon oxide layer provides a third tensile stress to make the wafer bend to the back side.

### Claim 2 (depends on 1)

The warpage-reducing semiconductor structure of claim 1, wherein the first tensile stress is the same as a summation of the second tensile stress and the third tensile stress.

### Claim 3 (depends on 1)

The warpage-reducing semiconductor structure of claim 1, wherein the silicon oxide layer comprises tetraethyl orthosilicate (TEOS), silicon oxycarbide (SiCO) or silicon oxynitride (SiON).

### Claim 4

A warpage-reducing semiconductor structure, comprising:
a wafer comprising a front side and a back side;
a plurality of metal lines disposed at the front side, wherein the metal lines comprise a plurality of first input/output (I/O) metal elements disposed at the front side, and the plurality of first I/O metal elements provide a first tensile stress to make the wafer bend toward the front side;
a stress layer directly contacting the back side, wherein the stress layer comprises tetraethyl orthosilicate (TEOS), nitrogen-doped silicon carbide (SiC:N), silicon oxycarbide (SiCO) or silicon oxynitride (SiON);
a silicon nitride layer covering the stress layer, wherein the stress layer is sandwiched between the back side and the silicon nitride layer; and
a plurality of second I/O metal elements disposed at the back side, wherein the plurality of second I/O metal elements provide a second tensile stress to make the wafer bend toward the back side, the second tensile stress is smaller than the first tensile stress, the stress layer is disposed between the plurality of second I/O metal elements and the back side, and the stress layer provides a third tensile stress to make the wafer bend toward the back side.

### Claim 5 (depends on 4)

The warpage-reducing semiconductor structure of claim 4, wherein the first tensile stress is the same as a summation of the second tensile stress and the third tensile stress.

### Claim 6

A fabricating method of a warpage-reducing semiconductor structure, comprising:
providing a wafer comprising a front side and a back side, wherein a plurality of semiconductor elements are disposed at the front side, the plurality of semiconductor elements comprise a plurality of first input/output (I/O) metal elements disposed at the front side, and the plurality of first I/O metal elements provide a first tensile stress to make the wafer bend toward the front side;
forming a silicon oxide layer directly contacting the back side;
forming a silicon nitride layer covering and contacting the silicon oxide layer, wherein the silicon oxide layer is sandwiched between the back side and the silicon nitride layer;
performing a UV light curing process, wherein during the UV light curing process, the UV light penetrates the silicon nitride layer to irradiate the silicon oxide layer; and
forming a plurality of second I/O metal elements disposed at the back side, wherein the plurality of second I/O metal elements provide a second tensile stress to make the wafer bend toward the back side, the second tensile stress is smaller than the first tensile stress, the silicon oxide layer and the silicon nitride layer are disposed between the plurality of second I/O metal elements and the back side, and the silicon oxide layer provides a third tensile stress to make the wafer bend to the back side.

### Claim 7 (depends on 6)

The fabricating method of a warpage-reducing semiconductor structure of claim 6, wherein the silicon nitride layer is a UV-transparent silicon nitride layer, and a refractive index of the silicon nitride layer is between 1.55 and 2.10.

### Claim 8 (depends on 6)

The fabricating method of a warpage-reducing semiconductor structure of claim 6, wherein the silicon oxide layer comprises tetraethyl orthosilicate (TEOS), silicon oxycarbide (SiCO) or silicon oxynitride (SiON).