# US 12,014,993 B2 · Package having redistribution layer structure with protective layer and method of fabricating the same

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- Number: US 12,014,993 B2
- Document ID: US12014993B2
- Status: Granted
- Kind: B2
- Application number: 17/341,314
- Filed: 2021-06-07
- Published: 2021-09-23
- Granted: 2024-06-18
- Earliest claimed: 2018-08-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Kuo-Chung Yee; Chun-Hui Yu
- Web page: https://patentgrep.com/patent/US12014993B2

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/016: {using moulds}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.

## Claims

### Claim 1

A method of fabricating a package, comprising:
providing a die with a contact thereon;
forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising:
forming a first dielectric material on the die;
forming a conductive feature in and partially on the first dielectric material, wherein the conductive feature has a top surface higher than a top surface of the first dielectric material;
after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers the top surface of the conductive feature and extends to cover the top surface of the first dielectric material;
forming a second dielectric material on the protective layer; and
performing a planarization process to remove a portion of the second dielectric material and a portion of the protective layer until the conductive feature is exposed; and
forming a plurality of conductive connectors to electrically connect the die through the RDL structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming a conductive feature comprises:
forming a via opening in the first dielectric material to expose the contact of the die;
forming a seed layer on the die to cover the via opening;
forming a photoresist layer on the seed layer;
patterning the photoresist layer to form a trench opening in the photoresist layer;
performing a plating process to form the conductive feature in the via opening and the trench opening; and
removing the photoresist layer and the seed layer not covered by the conductive feature.

### Claim 3 (depends on 2)

The method of claim 2, wherein after the performing the planarization process, the conductive feature comprises:
a plurality of first traces disposed on the first dielectric material and embedded in the second dielectric material, wherein a first portion of the seed layer is sandwiched between the plurality of first traces and the first dielectric material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the conductive feature further comprises:
a plurality of vias embedded in the first dielectric material; and
a plurality of second traces respectively disposed on the plurality of vias and embedded in the second dielectric material, wherein a second portion of the seed layer lining bottom surfaces and sidewalls of the plurality of vias, and the seed layer is free of between the plurality of vias and the plurality of second traces.

### Claim 5 (depends on 3)

The method of claim 3, wherein a portion of the protective layer extends between two adjacent first traces to form a U-shape in cross-section, and the two adjacent first traces are electrically isolated by the portion of the protective layer therebetween.

### Claim 6 (depends on 1)

The method of claim 1, wherein the protective layer comprises an inorganic dielectric material.

### Claim 7 (depends on 6)

The method of claim 6, wherein the inorganic dielectric material comprises an oxide, a nitride, an oxynitride, a carbide, or a combination thereof.

### Claim 8 (depends on 1)

The method of claim 1, wherein the protective layer and the second dielectric material have different materials.

### Claim 9 (depends on 1)

The method of claim 1, wherein the planarization process comprises a chemical-mechanical polishing (CMP) process, a mechanical grinding process, a fly cutting process or an etching back process.

### Claim 10

A package, comprising:
a die; and
a redistribution layer (RDL) structure electrically connected to the die, wherein the RDL structure comprises:
a dielectric layer comprising a first dielectric material and a second dielectric material over the first dielectric material;
a conductive feature electrically connected to the die, wherein the conductive feature comprises a plurality of first conductive patterns, and the plurality of first conductive patterns is disposed on and wholly above a top surface of the first dielectric material and embedded in the second dielectric material;
a first seed layer sandwiched between a bottom surface of each first conductive pattern of the plurality of first conductive patterns and the top surface of the first dielectric material, wherein the first seed layer is in direct contact with and completely covers the entire bottom surface of each first conductive pattern of the plurality of first conductive patterns; and
a first protective layer extending between two adjacent first conductive patterns and being in contact with the top surface of the first dielectric material, wherein the two adjacent first conductive patterns are electrically isolated by the first protective layer that extends over and covers sidewalls of the two adjacent first conductive patterns and sidewalls of the first seed layer.

### Claim 11 (depends on 10)

The package of claim 10, wherein the conductive feature further comprises a second conductive pattern and a third conductive pattern, the second conductive pattern is disposed in the second dielectric material, the third conductive pattern is disposed in the first dielectric material, and the second conductive pattern is disposed over and in contact with the third conductive pattern.

### Claim 12 (depends on 11)

The package of claim 11, wherein the RDL structure further comprises:
a second protective layer extending between the second conductive pattern and a corresponding first conductive pattern adjacent to the second conductive pattern to form a U-shape in cross-section; and
a second seed layer lining a bottom surface and a sidewall of the third conductive pattern, wherein a sidewall of the second conductive pattern is in contact with and covered by the second protective layer.

### Claim 13 (depends on 12)

The package of claim 12, wherein the first and second protective layers are conformal layers.

### Claim 14 (depends on 12)

The package of claim 12, wherein the first and second protective layers each comprises an inorganic dielectric material and the inorganic dielectric material comprises an oxide, a nitride, an oxynitride, a carbide, or a combination thereof.

### Claim 15 (depends on 10)

The package of claim 10, further comprising an encapsulant laterally encapsulating the die, wherein the RDL structure is disposed over the encapsulant and the die.

### Claim 16

A package structure, comprising:
a die having a front side and a back side;
an encapsulant laterally encapsulating a sidewall of the die; and
a first redistribution layer (RDL) structure disposed over the front side of the die and the encapsulant, wherein the first RDL structure comprises:
a dielectric layer comprising a first dielectric material and a second dielectric material over the first dielectric material;
a conductive feature electrically connected to the die, wherein the conductive feature comprises a plurality of first conductive patterns, the plurality of first conductive patterns is disposed on and wholly above a top surface of the first dielectric material and embedded in the second dielectric material; and
a first protective layer extending between two adjacent first conductive patterns and being in contact with the top surface of the first dielectric material, so as to form a U-shape in cross-section, wherein the first protective layer having a substantially same and uniform thickness to conformally covers sidewalls of the two adjacent first conductive patterns and the top surface of the first dielectric material,
wherein the plurality of first conductive patterns extend on the top surface of the first dielectric material without extending into the die, and the first protective layer covers the sidewalls of plurality of first conductive patterns without extending to contact bottom surfaces of the plurality of first conductive patterns.

### Claim 17 (depends on 16)

The package structure of claim 16, wherein the conductive feature further comprises a second conductive pattern and a third conductive pattern, the second conductive pattern is disposed in the second dielectric material, the third conductive pattern is disposed in the first dielectric material, and the second conductive pattern is disposed over and in contact with the third conductive pattern.

### Claim 18 (depends on 17)

The package structure of claim 17, wherein the RDL structure further comprises:
a second protective layer extending between the second conductive pattern and a corresponding first conductive pattern adjacent to the second conductive pattern to form a U-shape in cross-section;
a first seed layer sandwiched only between a bottom surface of each first conductive pattern of the plurality of first conductive patterns and the top surface of the first dielectric material; and
a second seed layer only lining a bottom surface and a sidewall of the third conductive pattern.

### Claim 19 (depends on 16)

The package structure of claim 16, further comprising:
a second RDL structure disposed over the back side of the die; and
a plurality of through interlayer vias (TIVs) aside the die and encapsulated by the encapsulant, wherein the TIVs is electrically connected to the first and second RDL structures.

### Claim 20 (depends on 16)

The package structure of claim 16, wherein the first protective layer comprises an inorganic dielectric material and the inorganic dielectric material comprises an oxide, a nitride, an oxynitride, a carbide, or a combination thereof.