# US 12,014,990 B2 · Composite interposer structure and method of providing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,990 B2 - Document ID: US12014990B2 - Status: Granted - Kind: B2 - Application number: 18/132,865 - Filed: 2023-04-10 - Published: 2023-08-03 - Granted: 2024-06-18 - Earliest claimed: 2019-11-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Adel Elsherbini; Shawna Liff; Johanna Swan; Gerald Pasdast - Web page: https://patentgrep.com/patent/US12014990B2 ## CPC - H10W 70/611: {for connecting multiple chips together} - H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 72/0198: {batch processes} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 80/016: {Cleaning} - H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/334: {Thermocompression bonding} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/792: {between multiple chips} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface. ## Claims ### Claim 1 An interposer comprising: a substrate comprising a glass; a first insulator structure and first interconnects therein; and a second insulator structure and second interconnects therein, wherein respective inorganic dielectrics of the first insulator structure and the second insulator structure adjoin each other at a material interface; wherein first contacts, to couple the interposer to a first IC chip, are in an arrangement which spans the material interface at a first side of the interposer; wherein second contacts, to couple the interposer to a second IC chip, are at a first surface of the first insulator structure, and are coupled to respective ones of the first contacts via the first interconnects; and wherein third contacts, at a second side of the interposer opposite the first side, are coupled to respective ones of the first contacts via the second interconnects. ### Claim 2 (depends on 1) The interposer of claim 1, wherein the first contacts comprise: fourth contacts at the first surface; and fifth contacts at a second surface of the second insulator structure; and wherein a first metallization feature pitch of the fourth contacts is smaller than a corresponding second metallization feature pitch of the fifth contacts. ### Claim 3 (depends on 2) The interposer of claim 2, wherein sixth contacts, to further couple the interposer to the second IC chip, are at the second surface; and wherein the third contacts comprise seventh contacts and eighth contacts, wherein the second interconnects are electrically coupled each between a respective one of the fifth contacts and a respective one of the seventh contacts, and wherein the interposer further comprises third interconnects in the second insulator structure, the third interconnects are electrically coupled each between a respective one of the sixth contacts and a respective one of the eighth contacts. ### Claim 4 (depends on 1) The interposer of claim 1, wherein the material interface comprises an artifact of one of a cut process, an etch process, a grind process, or a polish process. ### Claim 5 (depends on 1) The interposer of claim 1, wherein, at the first side, the first insulator structure comprises an artifact of one of a cut process, an etch process, a grind process, or a polish process. ### Claim 6 (depends on 1) The interposer of claim 1, wherein the first interconnects comprise a first metallization layer, wherein the second interconnects comprise a second metallization layer which, of any metallization layers of the second interconnects, is most aligned vertically with the first metallization layer, wherein a side of the first metallization layer is offset vertically from a corresponding side of the second metallization layer. ### Claim 7 (depends on 1) The interposer of claim 1, wherein a first dielectric material of the first insulator structure and a second dielectric material of the second insulator structure, the first dielectric material other than the second dielectric material, each extend to the material interface. ### Claim 8 (depends on 7) The interposer of claim 7, wherein the first dielectric material comprises a low-k dielectric. ### Claim 9 (depends on 1) The interposer of claim 1, further comprising active circuit components between the substrate and the first insulator structure, the active circuit components coupled, via the first interconnects, between the first contacts and the second contacts. ### Claim 10 (depends on 1) The interposer of claim 1, further comprising a semiconductor substrate between the first insulator structure and the substrate, wherein one of the first interconnects further extends through the semiconductor substrate. ### Claim 11 A method comprising: forming a first insulator structure and first interconnects therein, comprising bonding a chiplet to a substrate which comprises a glass; and forming on the substrate a second insulator structure and second interconnects therein, wherein respective inorganic dielectrics of the first insulator structure and the second insulator structure adjoin each other at a material interface; wherein first contacts of an interposer, the first contacts to couple the interposer to a first IC chip, are in an arrangement which spans the material interface at a first side of the interposer, wherein the interposer comprises the substrate, the first insulator structure, the second insulator structure, the first interconnects, and the second interconnects; wherein second contacts of the interposer, the second contacts to couple the interposer to a second IC chip, are at a first surface of the first insulator structure, and are coupled to respective ones of the first contacts via the first interconnects; and wherein third contacts of the interposer, the third contacts at a second side of the interposer opposite the first side, are coupled to respective ones of the first contacts via the second interconnects. ### Claim 12 (depends on 11) The method of claim 11, wherein the first contacts comprise: fourth contacts at the first surface; and fifth contacts at a second surface of the second insulator structure; wherein a first metallization feature pitch of the fourth contacts is smaller than a corresponding second metallization feature pitch of the fifth contacts. ### Claim 13 (depends on 11) The method of claim 11, wherein the material interface comprises an artifact of one of a cut process, an etch process, a grind process, or a polish process. ### Claim 14 (depends on 11) The method of claim 11, wherein the first interconnects comprise a first metallization layer, wherein the second interconnects comprise a second metallization layer which, of any metallization layers of the second interconnects, is most aligned vertically with the first metallization layer, wherein a side of the first metallization layer is offset vertically from a corresponding side of the second metallization layer. ### Claim 15 (depends on 11) The method of claim 11, wherein a first dielectric material of the first insulator structure and a second dielectric material of the second insulator structure, the first dielectric material other than the second dielectric material, each extend to the material interface. ### Claim 16 A system comprising: an interposer comprising: a substrate comprising a glass; a first insulator structure and first interconnects therein; and a second insulator structure and second interconnects therein, wherein respective inorganic dielectrics of the first insulator structure and the second insulator structure adjoin each other at a material interface; a first IC chip coupled to the interposer via first contacts which are in an arrangement which spans the material interface at a first side of the interposer; a second IC chip coupled to the interposer via second contacts, at a first surface of the first insulator structure, which are coupled to respective ones of the first contacts via the first interconnects; and a circuit board coupled to the interposer via third contacts, at a second side of the interposer opposite the first side, which are coupled to respective ones of the first contacts via the second interconnects. ### Claim 17 (depends on 16) The system of claim 16, wherein the first contacts comprise: fourth contacts at the first surface; and fifth contacts at a second surface of the second insulator structure; and wherein a first metallization feature pitch of the fourth contacts is smaller than a corresponding second metallization feature pitch of the fifth contacts. ### Claim 18 (depends on 16) The system of claim 16, wherein the first interconnects comprise a first metallization layer, wherein the second interconnects comprise a second metallization layer which, of any metallization layers of the second interconnects, is most aligned vertically with the first metallization layer, wherein a side of the first metallization layer is offset vertically from a corresponding side of the second metallization layer. ### Claim 19 (depends on 16) The system of claim 16, wherein a first dielectric material of the first insulator structure and a second dielectric material of the second insulator structure, the first dielectric material other than the second dielectric material, each extend to the material interface. ### Claim 20 (depends on 16) The system of claim 16, further comprising active circuit components between the substrate and the first insulator structure, the active circuit components coupled, via the first interconnects, between the first contacts and the second contacts.