# US 12,014,989 B2 · Device and method of very high density routing used with embedded multi-die interconnect bridge > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,989 B2 - Document ID: US12014989B2 - Status: Granted - Kind: B2 - Application number: 18/091,048 - Filed: 2022-12-29 - Published: 2023-05-04 - Granted: 2024-06-18 - Earliest claimed: 2022-08-15 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Robert Alan May; Wei-Lun Kane Jen; Jonathan L. Rosch; Islam A. Salama; Kristof Darmawikarta - Web page: https://patentgrep.com/patent/US12014989B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/00: Package configurations - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10W 70/63: Vias, e.g. via plugs - H10W 72/07252: {changes in structures or sizes} - H10W 72/227: {Multiple bumps having different sizes} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge. ## Claims ### Claim 1 A semiconductor device, comprising: alternating layers of dielectric material and metal; a bridge die above the alternating layers of dielectric material and metal; a plurality of conductive pillars adjacent to sides of the bridge die; a first insulating layer above the alternating layers of dielectric material and metal, the first insulating layer laterally between the plurality of conductive pillars and the bridge die; a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the plurality of conductive pillars, and over the bridge die, the second insulating layer having a bottommost surface; a plurality of vias in the second insulating layer, the plurality of vias coupled to the plurality of conductive pillars and to the bridge die, wherein the plurality of vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer; a first die coupled to the bridge die and to the plurality of conductive pillars; a second die coupled to the bridge die and to the plurality of conductive pillars; and a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die, and the third insulating layer intervening between the second insulating layer and the second die. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein one of the plurality of vias is offset from a central vertical access of a corresponding one the plurality of conductive pillars. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the plurality of vias is electrically connected to the plurality of conductive pillars and to the bridge die. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein a first portion of the plurality of vias coupled to the plurality of conductive pillars has a pitch greater than a pitch of a second portion of the plurality of vias coupled to the bridge die. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the first die is a CPU die, and the second die is a memory die. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the first die is a first CPU die, and the second die is a second CPU die. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the first die is a first memory die, and the second die is a second memory die. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the first die and the second die are electrically coupled to the bridge die and to the plurality of conductive pillars. ### Claim 9 A semiconductor device, comprising: a first metal layer; a first dielectric material layer above the first metal layer; a second metal layer above the first dielectric material layer; a second dielectric material layer above the second metal layer; a bridge die above the second dielectric material layer; first and second conductive pillars adjacent to a first side of the bridge die; third and fourth conductive pillars adjacent to a second side of the bridge die, the second side laterally opposite to the first side; a first insulating layer above the second dielectric material layer, the first insulating layer laterally between the first and second conductive pillars, laterally between the second conductive pillar and the bridge die, laterally between the bridge die and the third conductive pillar, and laterally between the third and fourth conductive pillars; a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the first conductive pillar, over and in direct contact with an uppermost surface of the second conductive pillar, over and in direct contact with an uppermost surface of the third conductive pillar, and over and in direct contact with an uppermost surface of the fourth conductive pillar, and over the bridge die, the second insulating layer having a bottommost surface; vias in the second insulating layer, the vias coupled to the first, second, third and fourth conductive pillars to the bridge die, wherein the vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer; a first die electrically coupled to the bridge die and to the first and second conductive pillars; a second die electrically coupled to the bridge die and to the third and fourth conductive pillars; and a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die, and the third insulating layer intervening between the second insulating layer and the second die. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein one of the vias is coupled to and offset from a central vertical access of the third conductive pillar. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein a first portion of the plurality of vias coupled to the first, second, third and fourth conductive pillars has a pitch greater than a pitch of a second portion of the plurality of vias coupled to the bridge die. ### Claim 12 (depends on 9) The semiconductor device of claim 9, wherein the first die is a first CPU die, and the second die is a second CPU die. ### Claim 13 A method of fabricating a semiconductor device, the method comprising: forming alternating layers of dielectric material and metal; providing a bridge die above the alternating layers of dielectric material and metal; forming a plurality of conductive pillars adjacent to sides of the bridge die; forming a first insulating layer above the alternating layers of dielectric material and metal, the first insulating layer laterally between the plurality of conductive pillars and the bridge die; forming a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the plurality of conductive pillars, and over the bridge die, the second insulating layer having a bottommost surface; forming a plurality of vias in the second insulating layer, the plurality of vias coupled to the plurality of conductive pillars and to the bridge die, wherein the plurality of vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer; coupling a first die to the bridge die and to the plurality of conductive pillars; coupling a second die to the bridge die and to the plurality of conductive pillars; and forming a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die, and the third insulating layer intervening between the second insulating layer and the second die. ### Claim 14 (depends on 13) The method of claim 13, wherein the one of the plurality of vias of offset from a central vertical access of a corresponding one the plurality of conductive pillars. ### Claim 15 (depends on 13) The method of claim 13, wherein the plurality of vias is electrically connected to the plurality of conductive pillars and to the bridge die. ### Claim 16 (depends on 13) The method of claim 13, wherein a first portion of the plurality of vias coupled to the plurality of conductive pillars has a pitch greater than a pitch of a second portion of the plurality of vias coupled to the bridge die. ### Claim 17 (depends on 13) The method of claim 13, wherein the first die is a CPU die, and the second die is a memory die. ### Claim 18 (depends on 13) The method of claim 13, wherein the first die is a first CPU die, and the second die is a second CPU die. ### Claim 19 (depends on 13) The method of claim 13, wherein the first die is a first memory die, and the second die is a second memory die. ### Claim 20 (depends on 13) The method of claim 13, wherein the first die and the second die are electrically coupled to the bridge die and to the plurality of conductive pillars.