# US 12,014,988 B2 · Semiconductor device having a graphene film and method for fabricating thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,014,988 B2
- Document ID: US12014988B2
- Status: Granted
- Kind: B2
- Application number: 17/358,752
- Filed: 2021-06-25
- Published: 2022-01-13
- Granted: 2024-06-18
- Earliest claimed: 2020-07-13
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jang Eun Lee; Min Joo Lee; Wan Don Kim; Hyun Bae Lee
- Web page: https://patentgrep.com/patent/US12014988B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10B 12/05: {Making the transistor}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/421: {Skip vias, i.e. vias that do not connect all metallization layers that they pass through}
- H10W 20/427: {Power or ground buses}
- H10W 20/438: {Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 20/048: {by using plasmas or gaseous environments, e.g. by nitriding}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/46: comprising air gaps
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.

## Claims

### Claim 1

A semiconductor device comprising:
a first level wiring disposed at a first metal level, the first level wiring including a first line wiring, a first insulating capping film, and a first side wall graphene film, the first insulating capping film extending along and contacting an upper surface of the first line wiring, and the first side wall graphene film extending along and contacting a side wall of the first line wiring;
an interlayer insulating film which covers the side wall of the first line wiring and a side wall of the first insulating capping film; and
a second level wiring disposed at a second metal level higher than the first metal level, the second level wiring including a second via connected to the first line wiring, and a second line wiring connected to the second via,
wherein the second via penetrates the first insulating capping film,
wherein the interlayer insulating film contacts the side wall of the first insulating capping film, and
wherein the first insulating capping film does not extend along an upper surface of the interlayer insulating film.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first level wiring further includes a first bottom graphene film extending along a bottom surface of the first line wiring.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first level wiring further includes a first upper surface graphene film extending along an upper surface of the first line wiring between the first line wiring and the first insulating capping film.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the second level wiring further includes a second side wall graphene film extending along a side wall of the second line wiring, and a second insulating capping film extending along an upper surface of the second line wiring, and
wherein the second line wiring and the second via have an integral structure.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising:
a third level wiring disposed at a third metal level between the first metal level and the second metal level, the third level wiring including a third line wiring and a third via,
the second via being directly connected to the first level wiring.

### Claim 6 (depends on 1)

The semiconductor device of claim 1,
wherein the second line wiring includes a wiring filling film, and a wiring barrier film extending along a side wall and a bottom surface of the wiring filling film,
wherein the wiring barrier film includes a conductive material including a metal, and
wherein a material included in the wiring filling film is different from a material included in the first line wiring.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising:
a third level wiring disposed at a third metal level higher than the second metal level,
wherein the third level wiring includes a third line wiring connected to the second line wiring, a third insulating capping film extending along an upper surface of the third line wiring, and a third side wall graphene film extending along a side wall of the third line wiring, and
wherein the third line wiring includes the same material as the first line wiring.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the interlayer insulating film includes an air gap disposed on at least one side of the first level wiring.

### Claim 9 (depends on 1)

The semiconductor device of claim 1,
wherein the first level wiring further includes a first via, and
wherein the first line wiring and the first via have an integral structure.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
a substrate disposed below the first level wiring; and
a buried power rail at least partially buried inside the substrate,
the first via being connected to the buried power rail.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the first line wiring includes ruthenium (Ru).

### Claim 12

A semiconductor device comprising:
a first level wiring disposed at a first metal level, the first level wiring including a first line wiring, a first side wall graphene film, and a first bottom graphene film, the first bottom graphene film extending along and contacting a bottom surface of the first line wiring, and the first side wall graphene film extending along and contacting a side wall of the first line wiring; and
a second level wiring disposed at a second metal level higher than the first metal level, the second level wiring including a second via connected to the first line wiring, and a second line wiring connected to the second via,
wherein a thickness of the first side wall graphene film is greater than a thickness of the first bottom graphene film, and
wherein the first level wiring further includes a first upper surface graphene film extending along an upper surface of the first line wiring.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a thickness of the first upper surface graphene film is greater than or equal to a thickness of the first side wall graphene film.

### Claim 14 (depends on 12)

The semiconductor device of claim 12,
wherein the second level wiring further includes a second side wall graphene film extending along a side wall of the second line wiring, and a second insulating capping film extending along an upper surface of the second line wiring, and
wherein the second line wiring and the second via have an integral structure.

### Claim 15 (depends on 12)

The semiconductor device of claim 12,
wherein the second line wiring includes a wiring filling film, and a wiring barrier film extending along a side wall and a bottom surface of the wiring filling film,
wherein the wiring barrier film includes a conductive material including a metal, and
wherein a material included in the wiring filling film is different from a material included in the first line wiring.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first line wiring includes ruthenium (Ru), and the wiring filling film includes copper (Cu).

### Claim 17

A semiconductor device comprising:
a first level wiring disposed at a first metal level, the first level wiring including a first ruthenium line wiring, a first insulating capping film, a first side wall graphene film, and a first bottom graphene film, the first insulating capping film extending along an upper surface of the first ruthenium line wiring, the first side wall graphene film extending along a side wall of the first ruthenium line wiring, and the first bottom graphene film extending along a bottom surface of the first ruthenium line wiring;
an interlayer insulating film which covers a side wall of the first ruthenium line wiring and a side wall of the first insulating capping film; and
a second level wiring disposed at a second metal level higher than the first metal level, the second level wiring including a second via penetrating the first insulating capping film and connected to the first ruthenium line wiring, and a second line wiring connected to the second via,
wherein the interlayer insulating film contacts the side wall of the first insulating capping film, and
wherein the first insulating capping film does not extend along an upper surface of the interlayer insulating film.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a thickness of the first side wall graphene film is greater than a thickness of the first bottom graphene film.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the first level wiring further includes a first upper surface graphene film which extends along an upper surface of the first ruthenium line wiring, between the first ruthenium line wiring and the first insulating capping film.