# US 12,014,986 B2 · Method for preparing semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing lining layer

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- Number: US 12,014,986 B2
- Document ID: US12014986B2
- Status: Granted
- Kind: B2
- Application number: 17/716,124
- Filed: 2022-04-08
- Published: 2022-07-28
- Granted: 2024-06-18
- Earliest claimed: 2020-11-13
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Chin-Te Kuo
- Web page: https://patentgrep.com/patent/US12014986B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/034: {bottomless barrier, adhesion or liner layers}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/0552: {by diffusing metallic dopants to react with dielectrics}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4424: {Copper alloys}
- H10W 20/46: comprising air gaps
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present disclosure provides a method for preparing a semiconductor device structure. The method includes preparing a substrate having a pattern-dense region and a pattern-loose region; forming a first conductive layer disposed over the substrate; forming a first dielectric layer disposed over the first conductive layer; etching the first dielectric layer to form a first opening and a second opening exposing the first conductive layer; forming a first lining layer and a first conductive plug in the first opening and a second conductive plug in the second opening, wherein the first lining layer comprises manganese (Mn), the first conductive plug comprises copper (Cu), and the first conductive plug and the second plug are surrounded by the first lining layer; and forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer, wherein the second conductive layer comprises copper (Cu).

## Claims

### Claim 1

A method for preparing a semiconductor device structure, comprising:
preparing a substrate having a pattern-dense region and a pattern-loose region;
forming a first conductive layer disposed over the substrate;
forming a first dielectric layer disposed over the first conductive layer;
etching the first dielectric layer to form a first opening and a second opening exposing the first conductive layer, wherein the first opening and the second opening have different aspect ratios;
forming a first lining layer and a first conductive plug in the first opening and a second conductive plug in the second opening, wherein the first conductive plug and the second conductive plug are surrounded by the first lining layer, wherein forming the first lining layer comprises:
extending the first lining layer from the pattern-dense region to the pattern-loose region;
disposing a first portion of the first lining layer under the first conductive plug; and
disposing a second portion of the first lining layer under the second conductive plug, wherein the first portion and the second portion of the first lining layer have different thicknesses; and
forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer.

### Claim 2 (depends on 1)

The method for preparing a semiconductor device structure of claim 1,
wherein the first conductive layer comprises copper (Cu);
wherein the first lining layer comprises manganese (Mn); and
wherein the second conductive layer comprises copper (Cu).

### Claim 3 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein forming the first lining layer comprises:
forming a first sub-lining layer over a top surface of the first dielectric layer and bottom surfaces of the first opening and the second opening; and
forming a second sub-lining layer over the first sub-lining layer to directly contact with the first conductive plug and the second conductive plug.

### Claim 4 (depends on 1)

The method for preparing a semiconductor device structure of claim 1,
wherein a width of the second opening is greater than a width of the first opening.

### Claim 5 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein a depth of the second opening is equal to a depth of the first opening.

### Claim 6 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein a height of the second conductive plug is greater than a height of the first conductive plug.

### Claim 7 (depends on 6)

The method for preparing a semiconductor device structure of claim 6, wherein a width of the second conductive plug is greater than a width of the first conductive plug.

### Claim 8

A method for preparing a semiconductor device structure, comprising:
preparing a substrate having a pattern-dense region and a pattern-loose region;
forming a first conductive layer over the substrate;
forming a first dielectric layer over the first conductive layer;
etching the first dielectric layer to form a first opening exposing the first conductive layer;
forming a first lining layer and a first conductive plug in the first opening, wherein the first conductive plug is surrounded by the first lining layer;
forming a second conductive layer over the first dielectric layer to cover the first lining layer and the first conductive plug in the first opening;
forming a second dielectric layer over the second conductive layer;
etching the second dielectric layer to form a second opening exposing the second conductive layer, wherein a bottom surface of the second opening is formed at a top surface of the second conductive layer; and
forming a second lining layer and a second conductive plug in the second opening, wherein the second conductive plug is surrounded by the second lining layer, wherein the second lining layer is formed on a top surface of the second dielectric layer and the bottom surface of the second opening;
wherein forming the second lining layer comprises:
forming a first sub-lining layer over the top surface of the second dielectric layer, wherein sidewalls and the bottom surface of the second opening are covered by the first sub-lining layer, and wherein the first sub-lining layer comprises manganese silicon (MnSi); and
forming a second sub-lining layer over the first sub-lining layer, wherein the second sub-lining layer comprises copper manganese (CuMn).