# US 12,014,983 B2 · Assemblies having conductive interconnects which are laterally and vertically offset relative to one another and methods of forming assemblies having conductive interconnects which are laterally and vertically offset relative to one another

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- Number: US 12,014,983 B2
- Document ID: US12014983B2
- Status: Granted
- Kind: B2
- Application number: 17/947,038
- Filed: 2022-09-16
- Published: 2023-01-19
- Granted: 2024-06-18
- Earliest claimed: 2020-07-10
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Raju Ahmed; Radhakrishna Kotti; David A. Kewley; Dave Pratt
- Web page: https://patentgrep.com/patent/US12014983B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10B 61/10: {comprising components having two electrodes, e.g. diodes or MIM elements}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10W 20/42: Vias, e.g. via plugs
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

## Claims

### Claim 1

An integrated assembly, comprising:
a base comprising circuitry;
a first memory level over the base and comprising a first conductive structure, the first conductive structure comprising a first region laterally spaced from a second region;
a first conductive interconnect coupling the first region of the first conductive structure and with the circuitry;
a second conductive interconnect extending upwardly from the second region of the first conductive structure; and
a second memory level over the first memory level and comprising a second conductive structure coupled with the circuitry through at least the first and second conductive interconnects and the first conductive structure.

### Claim 2 (depends on 1)

The integrated assembly of claim 1 further comprising:
a third conductive interconnect extending upwardly from the second conductive structure and directly over the first region of the first conductive structure; and
a third memory level over the second memory level and comprising a third conductive structure; the third conductive structure being coupled with the circuitry through at least the first, second and third conductive interconnects and the first and second conductive structures.

### Claim 3 (depends on 1)

The integrated assembly of claim 1 wherein the first conductive interconnect, the second conductive interconnect, the first conductive structure, and the second conductive structure are all compositionally the same as one another.

### Claim 4 (depends on 1)

The integrated assembly of claim 1 wherein at least one of the first conductive interconnect, the second conductive interconnect, the first conductive structure, and the second conductive structure is compositionally different from another of the first conductive interconnect, the second conductive interconnect, the first conductive structure, and the second conductive structure.

### Claim 5 (depends on 1)

The integrated assembly of claim 1 wherein the first and second conductive interconnects are compositionally different from the first and second conductive structures.

### Claim 6

An integrated assembly, comprising:
logic circuitry;
first memory circuitry over the logic circuitry, a first conductive line associated with the first memory circuitry;
second memory circuitry over the first memory circuitry, a second conductive line associated with the second memory circuitry;
a first conductive interconnect coupling the first conductive line with the logic circuitry; and
a second conductive interconnect laterally spaced from the first conductive interconnect and coupling the second conductive line with the logic circuitry through a path which includes the first and second conductive interconnects, and a region of the first conductive line.

### Claim 7 (depends on 6)

The integrated assembly of claim 6 wherein the first conductive line extends laterally across the first memory circuitry, wherein the first conductive interconnect is outward of a first side of the first memory circuitry, and wherein the second conductive interconnect is outward of an opposing second side of the first memory circuitry.

### Claim 8 (depends on 6)

The integrated assembly of claim 6 wherein the first and second conductive lines are first and second sense/access lines, respectively.

### Claim 9 (depends on 6)

The integrated assembly of claim 6 wherein the first conductive interconnect projects into the first conductive line and is of a different composition than the first conductive line.