US 12,014,982 B2Granted

Integrated circuit device and method

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsCheng-Yu Lin, Jung-Chan Yang, Hui-Zhong Zhuang, Sheng-Hsiung Chen, Kuo-Nan Yang, Chih-Liang Chen, Lee-Chung Lu

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Abstract

An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

Claims20

Dependent claims

An integrated circuit (IC) device, comprising:

a substrate;
and
a first cell and a second cell over the substrate, the first cell adjacent the second cell, each of the first cell and the second cell comprising at least one active region and at least one gate region extending across the at least one active region,
wherein
the first cell comprises a first input/output (TO) pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis transverse to the first axis,
the second cell comprises a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern, and
the first metal layer further comprises a first connecting pattern along the first track and connecting the first IO pattern of the first cell and a second IO pattern of the second cell, wherein the second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

4 more elements

A method, comprising:

generating a layout diagram of an integrated circuit (IC) device;
and
manufacturing the IC device based on the generated layout diagram,
wherein
said generating the layout diagram comprises:
placing a first cell adjacent a second cell in the layout diagram, each of the first cell and the second cell comprising at least one active region and at least one gate region extending across the at least one active region, wherein the first cell comprises a first input/output (TO) pattern, the second cell comprises a second IO pattern corresponding to the first IO pattern, and the first IO pattern and the second IO pattern are in a first metal layer and aligned along a first axis;
and
routing, in the first metal layer, a connecting pattern between the first IO pattern and the second IO pattern, wherein the connecting pattern is contiguous to, and aligned along the first axis with, both of the first IO pattern and the second IO pattern, and
the first metal layer is a metal-zero (M0) layer or a back-side-metal-zero (M0_B) layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/463,203Filed 31 Aug 2021
Published: US 2023/0068280 A12 Mar 2023
Granted: 18 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10W 20/43
Characterised by their conductive parts: layouts of interconnections
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/394
Circuit design at the physical level: routing