# US 12,014,980 B2 · Semiconductor device

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- Number: US 12,014,980 B2
- Document ID: US12014980B2
- Status: Granted
- Kind: B2
- Application number: 18/446,524
- Filed: 2023-08-09
- Published: 2024-01-25
- Granted: 2024-06-18
- Earliest claimed: 2020-05-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Suhyun Bark; Kyeongbeom Park; Jongmin Baek; Jangho Lee; Wookyung You; Deokyoung Jung
- Web page: https://patentgrep.com/patent/US12014980B2

## CPC

- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/42: Vias, e.g. via plugs
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/43: Layouts of interconnections
- H10W 20/432: {comprising crossing interconnections}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
forming a transistor on a substrate;
forming a first interlayer insulating layer on the transistor;
forming a lower interconnection line in an upper portion of the first interlayer insulating layer;
forming an etch stop layer on the first interlayer insulating layer and the lower interconnection line;
forming a surface treatment region in the etch stop layer by applying photon energy to a surface of the etch stop layer;
selectively forming an etch stop pattern on the surface treatment region of the etch stop layer;
forming a second interlayer insulating layer on the etch stop pattern and the etch stop layer;
forming an interconnection line hole in an upper portion of the second interlayer insulating layer;
forming a via hole penetrating the etch stop pattern and the etch stop layer and exposing a top surface of the lower interconnection line; and
forming an upper interconnection line in the interconnection line hole and the via hole.

### Claim 2 (depends on 1)

The method of claim 1, wherein a first concentration of carbon in the surface treatment region is lower than a second concentration of carbon in another region of the etch stop layer different than the surface treatment region.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first concentration of carbon in the surface treatment region ranges from about 1 at % to about 5 at %, and
wherein the second concentration of carbon in the another region of the etch stop layer ranges from about 10 at % to about 25 at %.

### Claim 4 (depends on 1)

The method of claim 1, wherein the photon energy includes extreme ultraviolet (EUV) light.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming of the etch stop layer comprises:
forming a first etch stop layer on a top surface of the first interlayer insulating layer; and
forming a second etch stop layer on the first etch stop layer,
wherein a first thickness of the first etch stop layer is less than a second thickness of the second etch stop layer, and
wherein a first dielectric constant of the etch stop pattern is greater than a second dielectric constant of the second etch stop layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein a third dielectric constant of the first etch stop layer is greater than the second dielectric constant of the second etch stop layer, and
wherein the surface treatment region comprises a hydrophilic surface and another region of the etch stop layer comprises a hydrophobic surface.

### Claim 7 (depends on 5)

The method of claim 5, wherein the surface treatment region is formed in the second etch stop layer.

### Claim 8

A method of manufacturing a semiconductor device comprising:
forming a transistor on a substrate;
forming a first interlayer insulating layer on the transistor;
forming a lower interconnection line in an upper portion of the first interlayer insulating layer;
forming an etch stop layer on the first interlayer insulating layer and the lower interconnection line;
forming a first surface treatment region and a second surface treatment region that are adjacent to opposing sides of the lower interconnection line, respectively, and formed in the etch stop layer;
selectively forming a first etch stop pattern and a second etch stop pattern on the first and second surface treatment regions, respectively, the first and second etch stop patterns defining a groove;
forming a second interlayer insulating layer on the first and second etch stop patterns and the etch stop layer;
forming an interconnection line hole in an upper portion of the second interlayer insulating layer;
forming a via hole penetrating the etch stop layer along the groove and exposing a top surface of the lower interconnection line; and
forming an upper interconnection line in the interconnection line hole and the via hole.

### Claim 9 (depends on 8)

The method of claim 8, wherein a first concentration of carbon in the first and second surface treatment regions is lower than a second concentration of carbon in another region of the etch stop layer different than the first and second surface treatment regions.

### Claim 10 (depends on 8)

The method of claim 8, wherein a first dielectric constant of each of the first and second etch stop patterns is greater than a second dielectric constant of the etch stop layer.

### Claim 11 (depends on 8)

The method of claim 8, wherein the forming of the first and second surface treatment regions comprises selectively applying photon energy to a first region and a second region of the etch stop layer.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the via hole exposes a first sidewall of the first etch stop pattern and a second sidewall of the second etch stop layer,
wherein the first sidewall faces the second sidewall, and
wherein the groove is defined between the first sidewall and the second sidewall.

### Claim 13

A method of manufacturing a semiconductor device comprising:
forming a transistor on a substrate;
forming a first interlayer insulating layer on the transistor;
forming a lower interconnection line in an upper portion of the first interlayer insulating layer;
forming an etch stop layer on the first interlayer insulating layer and the lower interconnection line;
forming an etch stop pattern on a surface treatment region of the etch stop layer;
forming a second interlayer insulating layer on the etch stop pattern and the etch stop layer;
forming an interconnection line hole in an upper portion of the second interlayer insulating layer;
forming a via hole penetrating the etch stop pattern and the etch stop layer and exposing a top surface of the lower interconnection line; and
forming an upper interconnection line in the interconnection line hole and the via hole,
wherein the via hole exposing the etch stop pattern has a first width in a first direction
wherein a maximum width of the etch stop pattern in the first direction is a second width, and
wherein the second width ranges from about 1.2 times to about 3 times the first width.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming the surface treatment region in the etch stop layer by applying photon energy to a surface of the etch stop layer.

### Claim 15 (depends on 13)

The method of claim 13, wherein a first dielectric constant of the etch stop pattern is greater than a second dielectric constant of the etch stop layer, and
wherein a first density of the etch stop pattern is lower than a second density of the etch stop layer.

### Claim 16 (depends on 13)

The method of claim 13, wherein a maximum thickness of the etch stop pattern is less than a thickness of the etch stop layer.

### Claim 17 (depends on 13)

The method of claim 13, wherein a first concentration of carbon in the surface treatment region is lower than a second concentration of carbon in another region of the etch stop layer different than the surface treatment region.

### Claim 18 (depends on 13)

The method of claim 13, wherein the maximum width of the etch stop pattern is confined within a width of the surface treatment region.

### Claim 19 (depends on 13)

The method of claim 13, wherein the forming of the etch stop layer comprises:
forming a first etch stop layer on a top surface of the first interlayer insulating layer; and
forming a second etch stop layer on the first etch stop layer,
wherein a first thickness of the first etch stop layer is less than a second thickness of the second etch stop layer, and
wherein a first dielectric constant of the etch stop pattern is greater than a second dielectric constant of the second etch stop layer.

### Claim 20 (depends on 9)

The method of claim 9, wherein the first concentration of carbon ranges from about 1 at % to about 5 at %, and
wherein the second concentration of carbon ranges from about 10 at % to about 25 at %,
wherein the first concentration of carbon increases with distance from the top surface of the etch stop layer toward the first interlayer insulating layer.