# US 12,014,979 B2 · Methods of forming semiconductor packages

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- Number: US 12,014,979 B2
- Document ID: US12014979B2
- Status: Granted
- Kind: B2
- Application number: 17/991,423
- Filed: 2022-11-21
- Published: 2023-03-23
- Granted: 2024-06-18
- Earliest claimed: 2018-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo Lung Pan; Shu-Rong Chun; Teng-Yuan Lo; Hung-Yi Kuo; Chih-Horng Chang; Tin-Hao Kuo; Hao-Yi Tsai
- Web page: https://patentgrep.com/patent/US12014979B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 74/014: {using batch processing}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/01371: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/07311: {Treating the bonding area before connecting, e.g. by applying flux or cleaning}
- H10W 72/07355: {changes in materials}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

## Claims

### Claim 1

A method comprising:
performing a plasma treatment process on a dielectric layer to thin the dielectric layer and to form hydroxyl groups dangling from a surface of the dielectric layer;
adhering an integrated circuit die to the surface of the dielectric layer;
dispensing an encapsulant around the integrated circuit die and on the surface of the dielectric layer, the encapsulant comprising a nucleophile;
curing the encapsulant to form covalent bonds between the nucleophile and the hydroxyl groups; and
forming a redistribution structure on the encapsulant, the redistribution structure comprising redistribution lines connected to the integrated circuit die.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
sputtering a metal into the dielectric layer; and
performing an etching process to remove the metal from the dielectric layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the etching process does not thin the dielectric layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein the etching process is a wet etch performed with hydrofluoric acid.

### Claim 5 (depends on 1)

The method of claim 1, wherein the plasma treatment process is a dry etch performed with oxygen.

### Claim 6 (depends on 1)

The method of claim 1, wherein adhering the integrated circuit die to the surface of the dielectric layer comprises:
dispensing an adhesive on the surface of the dielectric layer, the adhesive comprising the nucleophile.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
connecting a package substrate to the redistribution structure with a conductive connector, the conductive connector overlapping an edge or a corner of the integrated circuit die.

### Claim 8 (depends on 1)

The method of claim 1 further comprising:
depositing the dielectric layer on a metallization pattern; and
connecting a memory package to the metallization pattern with a conductive connector, the conductive connector overlapping an edge or a corner of the integrated circuit die.

### Claim 9

A method comprising:
depositing a seed layer on a surface of a dielectric layer;
plating a conductive material on the seed layer;
etching exposed portions of the seed layer, residual portions of the seed layer remaining buried in the dielectric layer;
performing a plasma treatment process on the dielectric layer to expose the residual portions of the seed layer and to form hydroxyl groups dangling from the surface of the dielectric layer;
removing the residual portions of the seed layer exposed by the plasma treatment process;
dispensing an encapsulant on the surface of the dielectric layer, the encapsulant comprising a nucleophile; and
curing the encapsulant to form covalent bonds between the nucleophile and the hydroxyl groups.

### Claim 10 (depends on 9)

The method of claim 9, wherein the plasma treatment process is a dry etch performed with oxygen.

### Claim 11 (depends on 9)

The method of claim 9, wherein removing the residual portions of the seed layer comprises performing an etching process with hydrofluoric acid.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dielectric layer is thinned by the plasma treatment process, and the dielectric layer is not thinned by the etching process.

### Claim 13 (depends on 9)

The method of claim 9 further comprising:
depositing the dielectric layer on a metallization pattern;
adhering an integrated circuit die to the surface of the dielectric layer; and
forming a conductive connector connected to the metallization pattern, the conductive connector overlapping an edge of the integrated circuit die.

### Claim 14 (depends on 9)

The method of claim 9 further comprising:
depositing the dielectric layer on a metallization pattern;
adhering an integrated circuit die to the surface of the dielectric layer; and
forming a conductive connector connected to the metallization pattern, the conductive connector overlapping a corner of the integrated circuit die.

### Claim 15

A method comprising:
forming a pit in a surface of a dielectric layer;
sputtering a metal into the pit;
thinning the dielectric layer to expose the metal in the pit;
removing the metal exposed by the thinning of the dielectric layer;
adhering an integrated circuit die to the surface of the dielectric layer;
forming an encapsulant around the integrated circuit die and on the surface of the dielectric layer; and
forming a redistribution structure on the encapsulant, the redistribution structure comprising redistribution lines connected to the integrated circuit die.

### Claim 16 (depends on 15)

The method of claim 15, wherein thinning the dielectric layer comprises etching the dielectric layer to thin the dielectric layer and to hydroxylate the surface of the dielectric layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein removing the metal comprises etching the metal with a wet etch that does not thin the dielectric layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein forming the encapsulant comprises bonding the encapsulant to the surface of the dielectric layer with covalent bonds.

### Claim 19 (depends on 15)

The method of claim 15 further comprising:
depositing the dielectric layer on a metallization pattern; and
forming a conductive connector connected to the metallization pattern, the conductive connector overlapping an edge of the integrated circuit die.

### Claim 20 (depends on 15)

The method of claim 15 further comprising:
depositing the dielectric layer on a metallization pattern; and
forming a conductive connector connected to the metallization pattern, the conductive connector overlapping a corner of the integrated circuit die.