# US 12,014,977 B2 · Interconnection structure, method of fabricating the same, and semiconductor package including interconnection structure

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- Number: US 12,014,977 B2
- Document ID: US12014977B2
- Status: Granted
- Kind: B2
- Application number: 18/199,824
- Filed: 2023-05-19
- Published: 2023-09-14
- Granted: 2024-06-18
- Earliest claimed: 2020-08-28
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ji-Seok Hong; Dongwoo Kim; Hyunah Kim; Un-Byoung Kang; Chungsun Lee
- Web page: https://patentgrep.com/patent/US12014977B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/00: Package configurations
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/685: comprising multiple insulating layers
- H10W 72/90: Bond pads, in general
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

## Claims

### Claim 1

A method of fabricating an interconnection structure, the method comprising:
forming a sacrificial pattern on a carrier substrate;
forming on the carrier substrate a first dielectric layer that has an opening, the sacrificial pattern being in the opening;
forming on the carrier substrate a first seed layer that conformally covers the sacrificial pattern, a top surface of the first dielectric layer, and an inner lateral surface and a bottom surface of the opening;
forming on the first seed layer a conductive layer that covers the first dielectric layer and fills the opening;
performing on the conductive layer a planarization process to form a pad that remains in the opening and to selectively remove the first seed layer from the top surface of the first dielectric layer;
forming a second dielectric layer on the first dielectric layer; and
forming a wiring pattern that penetrates the second dielectric layer and is coupled to the pad.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, before forming the first dielectric layer, forming on the carrier substrate a second seed layer that conformally covers the sacrificial pattern and a top surface of the carrier substrate,
wherein, in the opening, the first seed layer is in contact with the second seed layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second seed layer extends between the sacrificial pattern and the first seed layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein, beside the sacrificial pattern, the second seed layer extends between the carrier substrate and the first seed layer.

### Claim 5 (depends on 2)

The method of claim 2, further comprising:
removing the carrier substrate to expose the second seed layer and the sacrificial pattern;
performing on the second seed layer a planarization process to selectively remove the second seed layer from a bottom surface of the first dielectric layer; and
removing the sacrificial pattern.

### Claim 6 (depends on 5)

The method of claim 5, wherein, after the planarization process, a lowermost end of the second seed layer is located at a level the same as a level of the bottom surface of the first dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the pad includes:
a base part on a top surface of the sacrificial pattern; and
a sidewall part that extends from the base part along a lateral surface of the sacrificial pattern.

### Claim 8 (depends on 7)

The method of claim 7, wherein the pad has a U-shaped cross-section.

### Claim 9 (depends on 7)

The method of claim 7, wherein a width of the sidewall part is about 5% to about 20% of a width of the opening.

### Claim 10 (depends on 1)

The method of claim 1, wherein the first seed layer includes a metallic material whose ionization tendency is greater than an ionization tendency of a metallic material included in the pad.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
removing the carrier substrate to expose a bottom surface of the first dielectric layer, the first seed layer and the sacrificial pattern; and
removing the sacrificial pattern.

### Claim 12

A method of fabricating an interconnection structure, the method comprising:
forming a sacrificial pattern on a carrier substrate;
forming on the carrier substrate a first seed layer that conformally covers the sacrificial pattern;
forming on the carrier substrate a first dielectric layer that has an opening, the sacrificial pattern being in the opening;
forming on the carrier substrate a second seed layer that conformally covers the first seed layer, and an inner lateral surface of the opening;
forming on the second seed layer a conductive layer that fills the opening to form a pad;
forming a second dielectric layer on the first dielectric layer; and
forming a wiring pattern that penetrates the second dielectric layer and is coupled to the pad.

### Claim 13 (depends on 12)

The method of claim 12,
wherein the second seed layer conformally covers the sacrificial pattern, a top surface of the first dielectric layer, and the inner lateral surface and a bottom surface of the opening,
wherein the conductive layer covers the first dielectric layer and fills the opening, and
wherein the method further comprising performing on the conductive layer a planarization process to form the pad that remains in the opening and to selectively remove the second seed layer from the top surface of the first dielectric layer.

### Claim 14 (depends on 12)

The method of claim 12, wherein, in the opening, the first seed layer is in contact with the second seed layer.

### Claim 15 (depends on 12)

The method of claim 12, wherein, on the sacrificial pattern, the first seed layer extends between the sacrificial pattern and the second seed layer.

### Claim 16 (depends on 12)

The method of claim 12, wherein, adjacent to the sacrificial pattern, the first seed layer extends between the carrier substrate and the second seed layer.

### Claim 17 (depends on 12)

The method of claim 12, further comprising:
removing the carrier substrate to expose the first seed layer and the sacrificial pattern;
performing on the first seed layer a planarization process to selectively remove the first seed layer from a bottom surface of the first dielectric layer; and
removing the sacrificial pattern.

### Claim 18 (depends on 17)

The method of claim 17, wherein, after the planarization process, a lowermost end of the first seed layer is located at a level the same as a level of the bottom surface of the first dielectric layer.

### Claim 19 (depends on 12)

The method of claim 12, wherein the pad includes:
a base part on a top surface of the sacrificial pattern; and
a sidewall part that extends from the base part along a lateral surface of the sacrificial pattern.

### Claim 20 (depends on 19)

The method of claim 19, wherein a width of the sidewall part is about 5% to about 20% of a width of the opening.