# US 12,014,975 B2 · Semiconductor package

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- Number: US 12,014,975 B2
- Document ID: US12014975B2
- Status: Granted
- Kind: B2
- Application number: 17/453,243
- Filed: 2021-11-02
- Published: 2022-09-15
- Granted: 2024-06-18
- Earliest claimed: 2021-03-09
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jaegwon Jang; Kyoung Lim Suk; Minjun Bae
- Web page: https://patentgrep.com/patent/US12014975B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/655: Fan-out layouts
- H10W 70/656: Fan-in layouts
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/951: {Materials of bond pads}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern furthers include first fine wire patterns that are less wide than the wire portion of the second redistribution pattern.

## Claims

### Claim 1

A semiconductor package, comprising:
a redistribution substrate; and
a semiconductor chip disposed on a top surface of the redistribution substrate,
wherein the redistribution substrate comprises:
an insulating layer; and
a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern disposed in the insulating layer,
wherein the first to third redistribution patterns are sequentially stacked in a direction from a bottom surface of the redistribution substrate toward the top surface and are electrically connected to each other,
wherein each of the first to third redistribution patterns includes a wire portion that extends in a direction parallel to the top surface of the redistribution substrate,
each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate,
the second redistribution pattern further comprises first fine wire patterns that are less wide than the wire portion of the second redistribution pattern,
wherein a distance between adjacent first fine wire patterns ranges from 0.5 μm to 2 μm,
a width of the via portion of the first redistribution pattern is smallest at a level of a top surface of the via portion of the first redistribution pattern, and
a width of the via portion of the third redistribution pattern is smallest at a level of a bottom surface of the via portion of the third redistribution pattern.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein
a width of the via portion of the first redistribution pattern gradually decreases in a direction from the bottom surface of the redistribution substrate toward the top surface, and
a width of the via portion of the third redistribution pattern gradually increases in the direction from the bottom surface of the redistribution substrate toward the top surface.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein
an angle between the top surface and a side surface of the via portion of the first redistribution pattern ranges from 95° to 135°, and
an angle between the bottom and side surfaces of the via portion of the third redistribution pattern ranges from 95° to 135°.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein each of the first to third redistribution patterns includes a conductive pattern and a seed pattern that is disposed between the conductive pattern and the insulating layer,
the seed pattern of the first redistribution pattern is in contact with the conductive pattern of the second redistribution pattern, and
the seed pattern of the third redistribution pattern is in contact with the seed pattern of the second redistribution pattern.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the redistribution substrate further comprises:
a fourth redistribution pattern provided on the third redistribution pattern; and
a bonding pad provided on the fourth redistribution pattern,
wherein the fourth redistribution pattern comprises:
a wire portion that extends in a direction parallel to the top surface of the redistribution substrate; and
a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate and is in contact with the third redistribution pattern.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the fourth redistribution pattern further comprises second fine wire patterns that are less wide than the wire portion of the fourth redistribution pattern,
wherein the bonding pad comprises:
a via portion that penetrates the insulating layer and is in contact with the fourth redistribution pattern; and
a body portion disposed on the via portion.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the redistribution substrate further comprises an under-bump pattern disposed below the first redistribution pattern,
wherein the under-bump pattern comprises:
a via portion that penetrates the insulating layer and is in contact with the first redistribution pattern; and
a body portion disposed below the via portion.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein a side surface of the body portion of the under-bump pattern is perpendicular to the bottom surface of the redistribution substrate.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein a ratio of a width of a lowermost portion of the via portion of the first redistribution pattern to a width of an uppermost portion of the via portion of the third redistribution pattern ranges from 0.8 to 1.2.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein a width of each of the first fine wire patterns ranges from 0.5 μm to 2 μm.

### Claim 11

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip disposed on a top surface of the redistribution substrate, wherein the semiconductor chip includes a chip pad electrically connected to the redistribution substrate; and
a conductive terminal disposed on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
an insulating laver; and
a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern that are sequentially stacked in a direction from the bottom surface of the redistribution substrate toward the top surface and are electrically connected to each other,
wherein each of the first to third redistribution patterns includes a wire portion that extends in a direction parallel to the top surface of the redistribution substrate,
each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate,
the second redistribution pattern further includes first fine wire patterns that are less wide than the wire portion of the second redistribution pattern,
a width of the via portion of the first redistribution pattern gradually decreases in the direction from the bottom surface of the redistribution substrate toward the top surface, and
a width of the via portion of the third redistribution pattern gradually increases in the direction from the bottom surface of the redistribution substrate toward the top surface.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein
a width of the via portion of the first redistribution pattern is smallest at a level of a top surface of the via portion of the first redistribution pattern, and
a width of the via portion of the third redistribution pattern is smallest at a level of a bottom surface of the via portion of the third redistribution pattern.

### Claim 13 (depends on 11)

The semiconductor package of claim 11, wherein an angle between bottom and side surfaces of the second redistribution pattern is smaller than an angle between top and side surfaces of the via portion of the first redistribution pattern.

### Claim 14 (depends on 11)

The semiconductor package of claim 11, wherein each of the first to third redistribution patterns includes a conductive pattern and a seed pattern that is interposed between the conductive pattern and the insulating layer,
the seed pattern of the first redistribution pattern is in contact with the conductive pattern of the second redistribution pattern, and
the seed pattern of the third redistribution pattern is in contact with the seed pattern of the second redistribution pattern.

### Claim 15 (depends on 11)

The semiconductor package of claim 11, wherein a distance between adjacent first fine wire patterns ranges from 0.5 μm to 2 μm, and wherein a width of each of the first fine wire patterns ranges from 0.5 μm to 2 μm.

### Claim 16

A semiconductor package, comprising;
a redistribution substrate;
a semiconductor chip disposed on a top surface of the redistribution substrate, wherein the semiconductor chip includes a chip pad electrically connected to the redistribution substrate;
a mold layer that covers the semiconductor chip;
a bonding terminal interposed between the redistribution substrate and the chip pad; and
a conductive terminal disposed on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
an under-bump pattern;
an insulating layer disposed on the under-bump pattern;
a first redistribution pattern disposed on and in contact with the under-bump pattern;
a second redistribution pattern disposed on and in contact with the first redistribution pattern;
a third redistribution pattern disposed on and in contact with the second redistribution pattern;
a fourth redistribution pattern disposed on and in contact with the third redistribution pattern: and
a bonding pad disposed on and in contact with the fourth redistribution pattern,
wherein the first to fourth redistribution patterns are disposed in the insulating layer,
each of the first to fourth redistribution patterns includes a wire portion that extends in a direction parallel to the top surface of the redistribution substrate,
each of the first, third, and fourth redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate,
the second redistribution pattern further includes first fine wire patterns that are less wide than the wire portion of the second redistribution pattern,
the fourth redistribution pattern further includes second fine wire patterns that are less wide than the wire portion of the fourth redistribution pattern,
a distance between adjacent first fine wire patterns ranges from 0.5 μm to 2 μm,
a width of the via portion of the first redistribution pattern is smallest at a level of a top surface of the first redistribution pattern, and
a width of the via portion of the third redistribution pattern is smallest at a level of a bottom surface of the third redistribution pattern.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein
an angle between the top surface and a side surface of the via portion of the first redistribution pattern ranges from 95° to 135°, and
an angle between the bottom and side surfaces of the via portion of the third redistribution pattern ranges from 95° to 135°.

### Claim 18 (depends on 16)

The semiconductor package of claim 16, wherein an uppermost portion of the via portion of the third redistribution pattern and a lowermost portion of the via portion of the first redistribution pattern have substantially the same width.

### Claim 19 (depends on 16)

The semiconductor package of claim 16, wherein the under-bump pattern includes a plurality of under-bump patterns,
wherein each of the under-bump patterns comprises:
a via portion that penetrates the insulating layer and is in contact with the first redistribution pattern; and
a body portion disposed below the via portion,
wherein a distance between adjacent under-bump patterns ranges from 20 μm to 70 μm, and
a thickness of the body portion ranges from 10 μm to 20 μm.

### Claim 20 (depends on 19)

The semiconductor package of claim 19, wherein a side surface of the body portion of the under-bump pattern is perpendicular to the bottom surface of the redistribution substrate.