# US 12,014,973 B2 · Multi-die-package and method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,014,973 B2
- Document ID: US12014973B2
- Status: Granted
- Kind: B2
- Application number: 17/368,169
- Filed: 2021-07-06
- Published: 2021-10-28
- Granted: 2024-06-18
- Earliest claimed: 2017-11-17
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Andreas Riegler; Christian Fachmann
- Web page: https://patentgrep.com/patent/US12014973B2

## CPC

- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 70/047: {Attaching leadframes to insulating supports, e.g. for tape automated bonding [TAB]}
- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/811: {Multiple chips on leadframes}
- H02M 1/4225: {using a non-isolated boost converter}
- H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections}
- H02M 7/06: using discharge tubes without control electrode or semiconductor devices without control electrode
- H10W 70/427: {Bent parts}
- H10W 70/461: {specially adapted for cooling}
- H10W 72/07354: {changes in dispositions}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A method includes providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.

## Claims

### Claim 1

A method, comprising:
providing a processed first wafer having a front side, a back side and including a plurality of power semiconductor dies that have been implemented within the processed first wafer by processing its front side, each power semiconductor die having a first load terminal at the front side and a second load terminal at the back side;
providing an unprocessed second wafer made of an electrically insulating material and having a first side and a second side opposite thereof;
forming a plurality of recesses within the second wafer;
filling the plurality of recesses with a conductive material;
forming a stack by attaching, prior or subsequent to filling the plurality of recesses with the conductive material, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and
ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising configuring the second wafer as a coupling layer, wherein one of the first side and the second side of the second wafer is being configured to be coupled to a lead frame structure.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
separating the stack into a plurality of stack units; and
arranging at least one of the stack units within a package body of a package, wherein arranging the at least one stack unit includes electrically connecting the conductive material with the lead frame structure.

### Claim 4 (depends on 1)

The method of claim 1, wherein each first load terminal is arranged in accordance with a layout structure, and wherein forming the plurality of recesses within the second wafer is carried out in dependence of the layout structure.

### Claim 5 (depends on 1)

The method of claim 1, wherein each first load terminal is surrounded by an edge termination region of the respective power semiconductor die, and wherein, while attaching the second wafer to the front side of the first wafer, ensuring that the edge termination region is covered only by the insulating material of the second wafer.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the plurality of recesses within the second wafer comprises, before or after filling the plurality of recesses with the conductive material, transforming the recesses into pass-through passages.